ADV7190(Rev0) データシートの表示（PDF） - Analog Devices

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ADV7190
(Rev.:Rev0)

Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs

Analog Devices 

DETAILED DESCRIPTION OF FEATURES

Clocking:

Single 27 MHz Clock Required to Run the Device

4؋ Oversampling with Internal 54 MHz PLL

Square Pixel Operation

Advanced Power Management

Programmable Video Control Features:

Digital Noise Reduction

Pedestal level

Hue, Brightness, Contrast and Saturation

Clamping Output Signal

VBI (Vertical Blanking Interval)

Subcarrier Frequency and Phase

LUMA Delay

CHROMA Delay

Gamma Correction

Luma and Chroma Filters

Luma SSAF (Super Subalias Filter)

Average Brightness Detection

Field Counter

Interlaced/Noninterlaced Operation

Complete On-Chip Video Timing Generator

Programmable Multimode Master/Slave Operation

CGMS (Copy Generation Management System)

WSS (Wide Screen Signaling)

Macrovision 7.1 Rev

Closed Captioning Support

Teletext Insertion Port (PAL-WST)

2-Wire Serial MPU Interface

I2C Registers Synchronized to VSYNC

GENERAL DESCRIPTION

The ADV7190/ADV7191 is an integrated Digital Video Encoder

that converts digital CCIR-601/656 4:2:2 8-bit or 16-bit com-

ponent video data into a standard analog baseband television

signal compatible with worldwide standards.

ADV7190/ADV7191

Six DACs are available on the ADV7190/ADV7191, each of which

is capable of providing 4.33 mA of current. In addition to the

composite output signal there is the facility to output S-Video

(Y/C Video), RGB Video and YUV Video. All YUV formats

(Betacam, MII and (SMPTE/EBU N10) are supported.

Digital Noise Reduction allows improved picture quality in remov-

ing low amplitude, high frequency noise. The block diagram below

shows the DNR functionality in the two modes available.

Y DATA

INPUT

DNR MODE

DNR CONTROL

GAIN

BLOCK SIZE CONTROL CORING GAIN DATA

BORDER AREA

CORING GAIN BORDER

BLOCK OFFSET

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

SUBTRACT SIGNAL IN THRESHOLD

RANGE FROM ORIGINAL SIGNAL

FILTER OUTPUT

<THRESHOLD?

FILTER OUTPUT>

THRESHOLD

DNR OUT

Y DATA

INPUT

DNR SHARPNESS MODE

DNR CONTROL

GAIN

BLOCK SIZE CONTROL CORING GAIN DATA

BORDER AREA

CORING GAIN BORDER

BLOCK OFFSET

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

ADD SIGNAL ABOVE THRESHOLD

RANGE TO ORIGINAL SIGNAL

FILTER OUTPUT

>THRESHOLD?

MAIN SIGNAL PATH

FILTER OUTPUT<

THRESHOLD

DNR OUT

Figure 5. Block Diagram for DNR Mode and DNR Sharpness

Mode

PAL_NTSC VSO/CLAMP CSO_HSO

SCL SDA ALSB

HSYNC

VSYNC

BLANK

RESET

VIDEO TIMING

GENERATOR

CGMS/WSS

AND

CLOSED CAPTIONING

CONTROL

I2C MPU PORT

M

U

YUV-TO-RGB L

MATRIX

T

AND

I

TTX

TTXRQ

TELETEXT

INSERTION

BLOCK

10

YCrCb Y

DNR

10

Y

BRIGHTNESS

CONTROL

AND

ADD SYNC

AND

INTERPOLATOR

PROGRAMMABLE

LUMA FILTER

AND

SHARPNESS

FILTER

YUV LEVEL

P

CONTROL

L

BLOCK

E

X

E

R

TO

10

YUV U

MATRIX 10

V

AND

10

GAMMA U

CORRECTION 10

V

10 10 10

SATURATION

CONTROL

AND

ADD BURST

AND

PROGRAMMABLE

CHROMA

FILTER

MODULATOR

AND

HUE CONTROL

INTERPOLATOR

P0

DEMUX

P15

CLKIN

CLKOUT

REAL-TIME

ADV7190/ADV7191

CONTROL

PLL

CIRCUIT

SIN/COS

DDS

BLOCK

SCRESET/RTC/TR

Figure 4. Detailed Functional Block Diagram

REV. 0

–11–

I

N

T

E

R

P

O

L

A

T

IO

NR

T

E

R

P

O

L

A

T

O

R

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

DAC

CONTROL

BLOCK

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

DAC

CONTROL

BLOCK

DAC A

DAC B

DAC C

VREF

RSET2

COMP2

DAC D

DAC F

DAC E

RSET1

COMP1

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