CS5101 データシートの表示（PDF） - ON Semiconductor

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CS5101

Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters

ON Semiconductor 

CS5101

Theory of Operation

The CS5101 is designed to regulate voltages in multiple

output power supplies. Functionally, it is similar to a

magnetic amplifier, operating as a switch with a delayed

turn−on. It can be used with both single ended and dual

ended topologies.

The VFB voltage is monitored by the error amplifier EA.

It is compared to an internal reference voltage and the

amplified differential signal is fed through an inverting

amplifier into the buffer, BUF. The buffered signal is

compared at the PWM comparator with the ramp voltage

generated by capacitor CR. When the ramp voltage VR,

exceeds the control voltage VC, the output of the PWM

comparator goes high, latching its state through the LATCH,

the output stage transistor Q1 turns on, and the external

power switch, usually an N−FET, turns on.

SYNC Function

The SYNC circuit is activated at time t1 (Figure 3) when

the voltage at the SYNC pin exceeds the threshold level

(2.5V) of the SYNC comparator. The external ramp

capacitor CR is allowed to charge through the internal

current source I (200 mA). At time t2, the ramp voltage

intersects with the control voltage VC and the output of the

PWM comparator goes high, turning on the output stage and

the external power switch. At the same time, the PWM

comparator is latched by the RS latch, LATCH.

VSY

VSY

1

0V

2

VSY + VD

3 0V

VSY

4 0V

VC

VRAMP

VDS

VD

VS

VSY − VOUT

5 0V

VL1

VOUT + VD

VSY + VC

6 0V

VD

VG

Ground Level

(Gate doesn’t go t1 t2 t3 t4 t1

below GND)

Figure 3. Waveforms for CS5101. The Number to

the Left of Each Curve Refers to a Node On the

Application Diagram on Page 2.

The logic state of the LATCH can be changed only when

both the voltage level of the trailing edge of the power pulse

at the SYNC pin is less than the threshold voltage of the

SYNC comparator (2.5 V) and the RAMP voltage is less than

the threshold voltage of the RAMP comparator (1.65 V). On

the negative going transition of the secondary side pulse

VSY, gate G2 output goes high, resetting the latch at time t3.

Capacitor CR is discharged through transistor Q4. CR’s

output goes low disabling the output stage, and the external

power switch (an N−FET) is turned off.

RAMP Function

The value of the ramp capacitor CR is based on the

switching frequency of the regulator and the maximum duty

cycle of the secondary pulse VSY.

If the RAMP pin is pulled externally to 0.3 V or below, the

SSPR is disabled. Current drawn by the IC is reduced to less

than 100 mA, and the IC is in SLEEP mode.

FAULT Function

The voltage at the VCC pin is monitored by the

undervoltage lockout comparator with hysteresis. When

VCC falls below the UVL threshold, the 5.0 V reference and

all the circuitry running off of it is disabled. Under this

condition the supply current is reduced to less than 500 mA.

The VCC supply voltage is further monitored by the

VCC_OK comparator. When VCC is reduced below VREF

− 0.7 V, a fault signal is sent to gate G1. This fault signal,

which determines if VCC is absent, works in conjunction

with the ramp signal to disable the output, but only after the

current cycle has finished and the RS latch is reset.

Therefore this fault will not cause the output to turn off

during the middle of an on pulse, but rather will utilize

lossless turn−off. This feature protects the FET from

overvoltage stress. This is accomplished through gate G1 by

driving transistor Q4 on.

An additional fault signal is derived from the REF_OK

comparator. VREF is monitored so to disable the output

through gate G1 when the VREF voltage falls below the OK

threshold. As in the VCC_OK fault, the REF_OK fault

disables the output after the current cycle has been

completed. The fault logic will operate normally only when

VREF voltage is within the specification limits of REF_OK.

DRAIN Function

The drain pin, VD monitors the voltage on the drain of the

power switch and derives energy from it to keep the output

stage in an off state when VC or VCC is below the minimum

specified voltage.

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