CS61304A データシートの表示（PDF） - Cirrus Logic

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CS61304A

T1/E1 Line Interface

Cirrus Logic 

CS61304A

CS61304A

Power Supplies

RGND - Ground, Pin 22.

Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.

RV+ - Power Supply, Pin 21.

Power supply for all subcircuits except the transmit driver; typically +5 Volts.

TGND - Ground, Transmit Driver, Pin 14.

Power supply ground for the transmit driver; typically 0 Volts.

TV+ - Power Supply, Transmit Driver, Pin 15.

Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than

0.3 V.

Oscillator

XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.

A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or

2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying

XTALIN, Pin 9 to RV+ through a 1 kΩ resistor, and floating XTALOUT, Pin 10.

Overdriving the oscillator with an external clock is not supported.

Control

ACLKI - Alternate External Clock Input, Pin 1.

A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground.

During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator.

CLKE - Clock Edge, Pin 28. (Host Mode)

Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and

SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS

and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of

SCLK.

CS - Chip Select, Pin 26. (Host Mode)

This pin must transition from high to low to read or write the serial port.

INT - Receive Alarm Interrupt, Pin 23. (Host Mode)

Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing

"clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the

power supply through a resistor.

22

DSD1S5165P6PF21

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