CS61304A データシートの表示（PDF） - Cirrus Logic

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CS61304A

T1/E1 Line Interface

Cirrus Logic 

CS61304A

CS61304A

TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes)

Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined

by TCLK.

TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode)

Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting

TCODE high enables the AMI transmitter encoder .

Data

RCLK - Recovered Clock, Pin 8.

The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the

loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is

not present during LOS, RCLK is forced to the center frequency of the crystal oscillator.

RDATA - Receive Data - Pin 7. (Extended Hardware Mode)

Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the

line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK.

RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host

Modes)

The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS

and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines

the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse

(with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive

pulse received on the RRING pin generates a logic 1 on RNEG.

RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20.

The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up

transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data

and clock are recovered and output on RCLK and RPOS/RNEG or RDATA.

TCLK - Transmit Clock, Pin 2.

The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are

sampled on the falling edge of TCLK.

TDATA - Transmit Data, Pin 3. (Extended Hardware Mode)

Transmitter NRZ input data which passes through the line code encoder, and is then driven on to

the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK.

TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and

Host Modes)

Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and

TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a

positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted.

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DSD1S5165P6PF21

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