CS61304A データシートの表示（PDF） - Cirrus Logic
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CS61304A Datasheet PDF : 32 Pages
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CS61304A
CS61304A
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Receiver
RTIP/RRING Input Impedance
Sensitivity Below DSX (0dB = 2.4V)
Data Decision Threshold
T1, DSX-1
T1, DSX-1
T1, FCC Part 68 and E1
-
50k
-13.6
-
500
-
(Note 19)
60
65
(Note 20)
53
65
(Note 21)
45
50
-
Ω
-
dB
-
mV
70
% of peak
77
% of peak
55
% of peak
Allowable Consecutive Zeros before LOS
160
175
190
bits
Receiver Input Jitter Tolerance
10kHz - 100kHz
2kHz
10Hz and below
Loss of Signal Threshold
Jitter Attenuator
(Note 22)
0.4
-
6.0
-
300
-
-
UI
-
UI
-
UI
(Note 23) 0.25
0.30
0.50
V
Jitter Attenuation Curve Corner Frequency (Notes 16, 24)
-
3
Attenuation at 10kHz Jitter Frequency
(Notes 16, 24)
-
50
Attenuator Input Jitter Tolerance
(Notes 16, 24)
138
-
(Before Onset of FIFO Overflow or Underflow Protection)
-
Hz
-
dB
-
UI
Notes: 19. For input amplitude of 1.2 Vpk to 4.14 Vpk.
20. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+.
21. For input amplitude of 1.05 Vpk to 3.3 Vpk.
22. Jitter tolerance increases at lower frequencies. See Figure 11.
23. The analog input squelch circuit shall operate when the input signal amplitude above ground on the
RTIP and RRING pins falls within the range of 0.25V to 0.50V. Operation of the squelch results in
the recovery of zeros. During receive LOS, the RPOS, RNEG or RDATA outputs are forced low.
24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates
jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase
significantly when more than 138 UI’s are input to the attenuator. See discussion in the text section.
4
DSD1S5165P6PF21
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