CY62146DV30L データシートの表示（PDF） - Cypress Semiconductor
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CY62146DV30L Datasheet PDF : 11 Pages
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Pin Configuration[2, 3, 4]
VFBGA (Top View)
12
34
56
BLE OE A0 A1 A2 NC
A
I/O8 BHE A3 A4 CE I/O0
B
I/O9 I/O10 A5 A6 I/O1 I/O2
C
VSS I/O11 A17 A7 I/O3 Vcc
D
VCC I/O12 DNU A16 I/O4 Vss
E
I/O14 I/O13 A14 A15 I/O5 I/O6
F
I/O15 NC A12 A13 WE I/O7
G
NC A8 A9 A10 A11 NC
H
CY62146DV30
44 TSOP II (Top View)
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
I/O0 7
I/O1 8
I/O2 9
I/O3 10
VCC 11
VSS 12
I/O4 13
I/O5 14
I/O6 15
I/O7 16
WE 17
A17 18
A16 19
A15 20
A14 21
A13 22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 VSS
33 VCC
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 NC
27 A8
26 A9
25 A10
24 A11
23 A12
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CY62146DV30L
CY62146DV30LL
CY62146DV30L
CY62146DV30LL
CY62146DV30L
CY62146DV30LL
VCC Range (V)
Min.
Typ.[5]
Max.
2.20V
3.0
3.60
2.20V
3.0
3.60
2.20V
3.0
3.60
Speed
(ns)
45
55
70
Power Dissipation
Operating ICC (mA)
f = 1MHz
Typ.[5] Max.
f = fmax
Typ.[5] Max.
Standby ISB2 (µA)
Typ.[5] Max.
1.5
3
10
20
2
12
8
1.5
3
8
15
2
12
8
1.5
3
8
15
2
12
8
Notes:
2. NC pins are not internally connected on the die.
3. DNU pins have to be left floating or tied to VSS to ensure proper application.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05339 Rev. *A
Page 2 of 11
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