CY7C1219F データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY7C1219F Datasheet PDF : 15 Pages
| |||
Switching Characteristics Over the Operating Range (continued)[14, 15]
Parameter
tDS
tCES
Hold Times
tAH
tADH
tADVH
tWEH
tDH
tCEH
Description
Data Input Set-up Before CLK Rise
Chip Enable Set-up Before CLK Rise
Address Hold After CLK Rise
ADSP , ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW,BWE, BW[A:D] Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
166 MHz
Min. Max.
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Switching Waveforms
Read Timing[16]
tCYC
CY7C1219F
133 MHz
Min. Max.
Unit
1.5
ns
1.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
CLK
ADSP
ADSC
ADDRESS
GW, BWE,BW
[A:D]
CE
ADV
OE
Data IOut (Q)
tCH tCL
tADS tADH
tADS tADH
tAS tAH
A1
A2
tWES tWEH
tCES tCEH
A3
Burst continued with
new base address
Deselect
cycle
tADVS tADVH
ADV suspends burst
t
CLZ
High-Z
tCO
tOEHZ
Q(A1)
tOEV
tCO
tOELZ
tDOH
Q(A2) Q(A2 + 1)
Single READ
tCHZ
Q(A2 + 2)
Q(A2 + 3)
BURST READ
Q(A2) Q(A2 + 1) Q(A3)
Burst wraps around
to its initial state
DON’T CARE
UNDEFINED
Note:
16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05416 Rev. *A
Page 10 of 15
Share Link: 