CY7C1219F データシートの表示（PDF） - Cypress Semiconductor
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CY7C1219F Datasheet PDF : 15 Pages
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CY7C1219F
whenever a write cycle is detected, regardless of the state of
OE.
Burst Sequences
The CY7C1219F provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Both read and write burst operations
are supported.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Truth Table [2, 3, 4, 5, 6]
Operation
Deselected Cycle,
Power-down
Address
Used CE1 CE3 CE2 ZZ ADSP ADSC ADV WRITE OE
None H X X L
X
L
X
X
X
CLK
DQ
L-H three-state
Deselected Cycle,
Power-down
None L X L L
L
X
X
X
X
L-H three-state
Deselected Cycle,
Power-down
None L H X L
L
X
X
X
X
L-H three-state
Deselected Cycle,
Power-down
None L X L L
H
L
X
X
X
L-H three-state
Deselected Cycle,
Power-down
None L H X L
H
L
X
X
X
L-H three-state
ZZ Mode, Power-Down None X X X H
X
X
X
X
X
X three-state
Read Cycle, Begin Burst External L L H L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst External L L H L
L
X
X
X
H
L-H three-state
Write Cycle, Begin Burst External L L H L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst External L L H L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst External L L H L
H
L
X
H
H
L-H three-state
Read Cycle, Continue
Next X X X L
H
H
L
H
L
L-H
Q
Burst
Read Cycle, Continue
Burst
Next X X X L
H
H
L
H
H
L-H three-state
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals
(BWA, BWB, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05416 Rev. *A
Page 6 of 15
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