CY7C1219F データシートの表示（PDF） - Cypress Semiconductor
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CY7C1219F Datasheet PDF : 15 Pages
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Capacitance[9]
CIN
CCLK
CI/O
Parameter
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms
3.3V I/O Test Load
CY7C1219F
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 3.3V
Max.
Unit
5
pF
5
pF
5
pF
OUTPUT
Z0 = 50Ω
3.3V
OUTPUT
RL = 50Ω
5 pF
VT = 1.5V
(a)
INCLUDING
JIG AND
SCOPE
R = 317Ω
R = 351Ω
VDDQ
GND
ALL INPUT PULSES
10%
90%
≤ 1ns
90%
10%
≤1ns
(b)
(c)
Switching Characteristics Over the Operating Range [14, 15]
166 MHz
133 MHz
Parameter
tPOWER
Clock
Description
VDD(Typical) to the first Access[10]
Min. Max. Min. Max.
Unit
1
1
ms
tCYC
tCH
tCL
Output Times
Clock Cycle Time
Clock HIGH
Clock LOW
6.0
7.5
ns
2.5
3.0
ns
2.5
3.0
ns
tCO
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Set-up Times
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[11, 12, 13]
Clock to High-Z[11, 12, 13]
OE LOW to Output Valid
OE LOW to Output Low-Z[11, 12, 13]
OE HIGH to Output High-Z[11, 12, 13]
3.5
4.0
ns
2.0
2.0
ns
0
0
ns
3.5
4.0
ns
3.5
4.5
ns
0
0
ns
3.5
4.0
ns
tAS
Address Set-up Before CLK Rise
1.5
1.5
ns
tADS
ADSC, ADSP Set-up Before CLK Rise
1.5
1.5
ns
tADVS
ADV Set-up Before CLK Rise
1.5
1.5
ns
tWES
GW, BWE, BW[A : D] Set-up Before CLK Rise
1.5
1.5
ns
Notes:
9. Tested initially and after any design or process change that may affect these parameters.
10. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
11. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing reference level is 1.5V when VDDQ = 3.3V.
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05416 Rev. *A
Page 9 of 15
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