AD808-622BRRL データシートの表示（PDF） - Analog Devices

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AD808-622BRRL

Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming

Analog Devices 

AD808

Center Frequency Clamp (Figure 13)

An N-channel FET circuit can be used to bring the AD808

VCO center frequency to within ± 10% of 622 MHz when

SDOUT indicates a Loss of Signal (LOS). This effectively re-

duces the frequency acquisition time by reducing the frequency

error between the VCO frequency and the input data frequency

at clamp release. The N-FET can have “on” resistance as high

as 1 kΩ and still attain effective clamping. However, the chosen

N-FET should have greater than 10 MΩ “off” resistance and

less than 100 nA leakage current (source and drain) so as not to

alter normal PLL performance.

N_FET

CD

1 DATAOUTN

2 DATAOUTP

3 VCC2

4 CLKOUTN

VEE 16

SDOUT 15

AVCC2 14

PIN 13

5 CLKOUTP

NIN 12

6 VCC1

7 CF1

AVCC1 11

THRADJ 10

8 CF2 AD808 AVEE 9

Figure 13. Center Frequency Clamp Schematic

CD

0.047

0.10

0.47

PEAK

0.11

0.07

0.04

DIV

20.00m

RBW:

DIV

36.00m

START

STOP

30Hz ST: 3.07 min RANGE: R=

500.000Hz

100 000.000Hz

0, T=

0dBm

Figure14. Jitter Transfer vs. CD

C1 0.1␮F

R1 R2

100⍀ 100⍀

J1 C3 0.1␮F

DATAOUTN

DATAOUTP

J2 C4 0.1␮F

J3 C5 0.1␮F

CLKOUTN

CLKOUTP

J4

C6

0.1␮F

R3

100⍀

R4

100⍀

C2

0.1␮F

R9

154⍀

R5 100⍀

R6 100⍀

R10

154⍀

1

2

3

R7 100⍀ C7

4

R8 100⍀

5

R11

154⍀

6

C8 TP1

7

R12 CD

154⍀ TP2

8

50⍀ STRIP LINE

EQUAL LENGTH

DATAOUTN

VEE

DATAOUTP SDOUT

VCC2

AVCC2

CLKOUTN

PIN

CLKOUTP

NIN

VCC1

CF1

AVCC1

THRADJ

CF2 AD808 AVEE

TP7 TP8

16

15

14

C9

13

12

11

C10

10

RTHRESH

9

J5

SDOUT

C12

0.1␮F

R13

301⍀

TP5

TP6

R14

49.9⍀

R16 3.65k⍀

R15

49.9⍀ C13 0.1␮F J6

PIN

NIN

C14 0.1␮F J7

VECTOR PINS SPACED FOR RN55C

TYPE RESISTOR; COMPONENT

SHOWN FOR REFERENCE ONLY

NOTE:

C11

TP3 10␮F TP4

+5V GND

NOTE: INTERCONNECT RUN

UNDER DUT

VECTOR PINS SPACED THROUGH-HOLE

CAPACITOR ON VECTOR CUPS; COMPONENT

SHOWN FOR REFERENCE ONLY

C7–C10 ARE 0.1µF BYPASS CAPACITORS

RIGHT ANGLE SMA CONNECTOR

OUTER SHELL TO GND PLANE

ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT

TPxo TEST POINTS ARE VECTORBOARD K24A/M PINS

Figure 15. Evaluation Board Schematic

–8–

REV. 0

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