CXB1582Q データシートの表示（PDF） - Sony Semiconductor

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CXB1582Q

Fibre Channel Receiver

Sony Semiconductor 

CXB1582Q

Pin

No.

Symbol

Type

Typical pin

I/O voltage

36 LKDT∗

TTL

output

TTL level

Equivalent circuit

VCCT5

VCCT3

LKDT∗

VCCG

VEET

Description

PLL lock detection

signal output.

This pin outputs low

level when the PLL is

locked to the serial

data and high level

when the PLL

becomes unlocked.

37 SSEL1

38 SSEL0

TTL

input

TTL level

SSEL0

SSEL1

SOUT/SOUT∗ output

signal selection.

(See Table 1.)

VEET

VEET

VCCG

39 PDTEST

TTL

input

0V

PDTEST

Test.

Connect to VEEG.

VEET

VCCG

40

ECLKSEL∗

TTL

input

TTL high

level or 3.3V

ECLKSEL∗

VEET

–6–

VEET

External clock

selection.

When this pin is set

to low level, the clock

input to EXCLK is

used as the bit rate

clock.

VEET

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