DRF100 データシートの表示（PDF） - Microsemi Corporation
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DRF100 Datasheet PDF : 4 Pages
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The Function (FN, pin 3) is the invert or non-invert select Pin, it is Internally held high, Normally Non-inverting.
FN (pin 3)*
HIGH
HIGH
LOW
LOW
Truth Table *Referenced to SG
IN (pin 4)*
Function
HIGH
Non-Invert
LOW
Non-Invert
HIGH
Inverting
LOW
Inverting
OUTPUT
HIGH
LOW
LOW
HIGH
DRF100
Figure 2, DRF100 Test Circuit
The Test Circuit illustrated above was used to evaluate the DRF100 (available as an evaluation Board DRF100 / EVALSW.) The input control
signal is applied to the DRF100 via IN(4) and SG(5) pins using RG188. This provides excellent noise immunity and control of the signal
ground currents.
The +VDD inputs (2,6) are by-passed (C1, C2, C4-C9), this is in addition to the internal by-passing mentioned previously. The capacitors used
for this function must be capable of supporting the RMS currents and frequency of the gate load.
Microsemi’s products are covered by one or more of U.S. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583
4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743 and foreign patents. US and Foreign patents pending. All Rights Reserved.
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