F25L004A(2007) データシートの表示（PDF） - [Elite Semiconductor Memory Technology Inc.
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F25L004A Datasheet PDF : 32 Pages
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ESMT
F25L004A
Table2 : F25L004A Block Protection Table
TOP
Protection Level
0
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
All Blocks
Status Register Bit
BP2
BP1
BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Protected Memory Area
Block Range
Address Range
None
None
Block 7
70000H – 7FFFFH
Block 6~7
60000H – 7FFFFH
Block 4~7
40000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
BOTTOM
Protection Level
0
Bottom 1/8
Bottom 1/4
Bottom 1/2
All Blocks
All Blocks
All Blocks
All Blocks
Status Register Bit
BP2
BP1
BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Protected Memory Area
Block Range
Address Range
None
None
Block 0
00000H – 0FFFFH
Block 0~1
00000H – 1FFFFH
Block 0~3
00000H – 3FFFFH
Block 0~7
00000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
BP2, P1, BP0 bits as long as WP is high or the
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-up, BP2,
BP1 and BP0 are set to1.
Block Protection Lock-Down (BPL)
WP pin driven low (VIL), enables the Block-Protection
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2007
Revision: 1.2 5/32
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