FC40SA50FKP データシートの表示（PDF） - Vishay Semiconductors

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FC40SA50FKP

Power MOSFET, 40 A

Vishay Semiconductors 

FC40SA50FKP

Vishay Semiconductors

Power MOSFET, 40 A

V(BR)DSS

tp

IAS

Fig. 12c - Unclamped Inductive Waveforms

VGS

1 mA

RL

D .U .T .

+

VDS

-

ID

Fig. 13a - Gate Charge Test Circuit

VGS V

QGS

VG

QG

QGD

Charge

Fig. 13b - Basic Gate Charge Waveform

D.U.T.

+

2

-

1

RG

+

Circuit layout considerations

• Low stray inductance

3

• Ground plane

• Low leakage inductance

current transformer

-

- 4+

• dV/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by duty factor "D"

• D.U.T. - Device under test

+

- VDD

Fig. 13c - Peak Diode Recovery dV/dt Test Circuit

www.vishay.com

6

For technical questions within your region, please contact one of the following: Document Number: 94542

DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com

Revision: 12-May-10

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