FM4005 データシートの表示（PDF） - Ramtron International Corporation
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FM4005 Datasheet PDF : 23 Pages
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Manual Reset
The /RST pin is bi-directional and allows the
FM4005 to filter and de-bounce a manual reset
switch. The /RST input detects an external low
condition and responds by driving the /RST signal
low for 100 ms. Note that an internal weak pull-up on
/RST eliminates the need for additional external
components.
MCU
Reset
Switch
RST
FM4005
Switch
Behavior
RST
FM4005
drives
100 ms
Figure 4. Manual Reset
Reset Flags
In case of a reset condition, a flag will be set to
indicate the source of the reset. A low VDD reset or
manual reset is indicated by the POR flag, register
09h bit 6. A watchdog reset is indicated by the WTR
flag, register 09h bit 7. Note that the bits are
internally set in response to reset sources, but they
must be cleared by the user. When the register is
read, it is possible that both flags are set if both have
occurred since the user last cleared them.
Early Power Fail Comparator
An early power fail warning can be provided to the
processor well before VDD drops out of spec. The
comparator is used to create a power fail interrupt
(NMI). This can be accomplished by connecting the
PFI pin to the unregulated power supply via a resistor
divider. An application circuit is shown below. The
voltage on the PFI input pin is compared to an
onboard 1.2V reference. When the PFI input voltage
drops below this threshold, the comparator will drive
the CAL/PFO pin to a low state. The comparator has
350 mV (max) of hysteresis to reduce noise
sensitivity, only for a rising PFI signal. For a falling
PFI edge, there is no hysteresis.
Rev. 2.3
Oct. 2006
FM4005
Regulator
VDD
FM4005
To MCU CAL/PFO
NMI input
+
- 1.2V ref
Figure 5. Comparator as a Power-fail Warning
The comparator is a general purpose device and its
application is not limited to the NMI function.
The comparator is not integrated into the special
function registers except as it shares its output pin
with the CAL output. When the RTC calibration
mode is invoked by setting the CAL bit (register 00h,
bit 2), the CAL/PFO output pin will be driven with a
512 Hz square wave and the comparator will be
ignored. Since most users only invoke the calibration
mode during production, this should have no impact
on system operations using the comparator.
Note: The maximum voltage on the comparator input PFI
is limited to 3.75V under normal operating conditions.
Event Counter
The FM4005 offers the user two battery-backed event
counters. The input pins CNT1 and CNT2 are
programmable edge detectors. Each controls a 16-bit
counter. When an edge occurs, the counters will
increment their respective registers. Counter 1 is
located in registers 0Dh and 0Eh. Counter 2 is
located in registers 0Fh and 10h. These register
values can be read anytime VDD is above VTP, and
they will be incremented as long as a valid VBAK
power source is provided. To read, set the RC bit
register 0Ch bit 3 to 1. This takes a snapshot of all
four counter bytes allowing a stable value even if a
count occurs during the read. The registers can be
written by software allowing the counters to be
cleared or initialized by the system. Counts are
blocked during a write operation. The two counters
can be cascaded to create a single 32-bit counter by
setting the CC control bit (register 0Ch). When
cascaded, the CNT1 input will cause the counter to
increment. CNT2 is not used in this mode.
The control bits for event counting are located in
register 0Ch. Counter 1 Polarity is bit C1P, bit 0;
Page 5 of 23
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