FM4005 データシートの表示（PDF） - Ramtron International Corporation

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FM4005

Integrated Processor Companion

Ramtron International Corporation 

FM4005

32.768 kHz

crystal

OSCEN

Oscillator

512 Hz

W

Clock

Divider

1 Hz

Update

Logic

CF

Years

8 bits

Months

5 bits

Date

6 bits

Days

3 bits

Hours

6 bits

Minutes

7 bits

Seconds

7 bits

User Interface Registers

R

Figure 7. Real-Time Clock Core Block Diagram

Calibration

When the CAL bit in register 00h is set to 1, the

clock enters calibration mode. In calibration mode,

the CAL/PFO output pin is dedicated to the

calibration function and the comparator output is

temporarily unavailable. Calibration operates by

applying a digital correction to the counter based on

the frequency error. In this mode, the CAL/PFO pin

is driven with a 512 Hz (nominal) square wave. Any

measured deviation from 512 Hz translates into a

timekeeping error. The user converts the measured

error in ppm and writes the appropriate correction

value to the calibration register. The correction

factors are listed in the table below. Positive ppm

errors require a negative adjustment that removes

pulses. Negative ppm errors require a positive

correction that adds pulses. Positive ppm adjustments

have the CALS (sign) bit set to 1, where as negative

ppm adjustments have CALS = 0. After calibration,

the clock will have a maximum error of ± 2.17 ppm

or ± 0.09 minutes per month at the calibrated

temperature.

The calibration setting is stored in a nonvolatile

register so is not lost should the backup source fail. It

is accessed with bits CAL.4-0 in register 01h. This

value only can be written when the CAL bit is set to a

1. To exit the calibration mode, the user must clear

the CAL bit to a 0. When the CAL bit is 0, the

CAL/PFO pin will revert to the comparator output

function.

Rev. 2.3

Oct. 2006

Page 7 of 23

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