TDA7580(2002) データシートの表示（PDF） - STMicroelectronics

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TDA7580
(Rev.:2002)

FM/AM digital IF sampling processor

STMicroelectronics 

TDA7580

PIN DESCRIPTION (continued)

N°

Name

30 RDS_CS

31 INT

32 ADDR_SD

33 RESETN

34 VDD

35 GND

36 TESTN

37 GPIO_SDO1

38 TST4_SDI0

39 TST1_SDI1

40 GNDH

41 VDDH

42 SDO0

43 SCLK_SCKT

44 LRCK_LRCKT

Type

Description

Notes

B RDS chip select. When RESETN rising, DSP1 GPIO5

If RDS_CS 0, the RDS’s SPI is selected; 5V tolerant

else RDS’s I2C

With internal pull_up, on

at reset

I DSP0 External Interrupt

5V tolerantWith internal

pull_up, on at reset

B IFS chip master (Low) or slave (High) DSP0 GPIO2

mode selection, latched in upon

5V tolerantWith internal

RESETN release. It selects the LSB of pull_down, on at reset

the I2C addresses.

Station Detector output

I Chip Hardware reset, active Low

5V tolerant

With internal pull_up

P Digital Power Supply

1.8V

G Digital Power Ground

I Test Enable pin, active Low

With internal pull_up

B DSP0 GPIO for Boot selection or Audio 5V tolerant

SAI0 output.

DSP0 GPIO3

With internal pull_up, on

at reset

B Audio SAI0 Data input or test selection 5V tolerant

pin in Test Mode

DSP0 GPIO5With

internal pull_up, on at

reset

B DSP0 GPIO for Boot selection or Audio 5V tolerant

SAI1 input. Test selection pin in Test

DSP0 GPIO4With

Mode.

internal pull_up, on at

reset

G 3.3V IO Ring Power Ground (Audio SAI,

ResetN, Test Pins)

P 3.3V IO Ring Power Supply (Audio SAI,

ResetN, Test Pins)

B Radio or Audio SAI0 data output

5V tolerant

With internal pull_up, on

at reset

B SAI0 Receive and Transmit bit clock

(master or slave with ASRC); SAI1

Transmit bit clock

5V tolerant

With internal pull_up, on

at reset

B SAI0 Receive and Transmit LeftRight 5V tolerant

clock (master or slave with ASRC); SAI1 With internal pull_up, on

Transmit LeftRight clock

at reset

After

Reset

Input

Input

Input

Input

Input

Output

Input

Input

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