FS6370 データシートの表示（PDF） - ON Semiconductor

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FS6370

EEPROM Programmable 3-PLL Clock Generator IC

ON Semiconductor 

FS6370

Figure 5: FS6370 to FS6377

7.2 Non-Programming Migration Path

If the design has solidified on a particular EEPROM programming pattern, the EEPROM pattern can be hard-coded into a ROM-based

device. For high-volume requirements, a ROM-based device offers significant cost savings over the FS6370. Contact an ON

Semiconductor sales representative for more detail.

8.0 I2C-bus Control Interface

This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to

be controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and

STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but

the master device determines which mode is activated. A device that sends data onto the bus is defined as the

transmitter, and a device receiving data as the receiver.

I2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of

VDD, while a logic-low corresponds to ground (VSS).

8.1 Bus Conditions

Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable

whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START

or STOP condition. The following bus conditions are defined by the I2C-bus protocol.

8.1.1. Not Busy

Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.

8.1.2. START Data Transfer

A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be

preceded by a START condition.

Rev. 3 | Page 8 of 28 | www.onsemi.com

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