DS21FT44 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS21FT44
Dallas Semiconductor -> Maxim Integrated
DS21FT44 Datasheet PDF : 110 Pages
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TABLE OF CONTENTS
DS21FT44/DS21FF44
1. MULTI-CHIP MODULE (MCM) DESCRIPTION.........................................................................1
2. MCM LEAD DESCRIPTION ............................................................................................................7
3. DS21FF44 (Four x Four) PCB LAND PATTERNS .......................................................................15
4. DS21FT44 (Four x Three) PCB Land Pattern................................................................................16
5. DS21Q42 DIE DESCRIPTION ........................................................................................................17
6. DS21Q44 INTRODUCTION ............................................................................................................18
7. DS21Q44 PIN FUNCTION DESCRIPTION ..................................................................................21
8. DS21Q44 REGISTER MAP .............................................................................................................27
9. PARALLEL PORT ...........................................................................................................................32
10. CONTROL, ID AND TEST REGISTERS......................................................................................32
11. STATUS AND INFORMATION REGISTERS .............................................................................41
12. ERROR COUNT REGISTERS........................................................................................................47
13. DS0 MONITORING FUNCTION ...................................................................................................49
14. SIGNALING OPERATION .............................................................................................................52
14.1 PROCESSOR BASED SIGNALING ............................................................................................................52
14.2 HARDWARE BASED SIGNALING ..............................................................................................................55
15. PER–CHANNEL CODE GENERATION AND LOOPBACK.....................................................56
15.1 TRANSMIT SIDE CODE GENERATION.....................................................................................................56
15.1.1 Simple Idle Code Insertion And Per–Channel Loopback....................................................................56
15.1.2 Per–Channel Code Insertion...............................................................................................................57
15.2 RECEIVE SIDE CODE GENERATION .......................................................................................................58
16. CLOCK BLOCKING REGISTERS................................................................................................59
17. ELASTIC STORES OPERATION..................................................................................................60
17.1 RECEIVE SIDE............................................................................................................................................61
17.2 TRANSMIT SIDE .........................................................................................................................................61
18. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION ......................................61
18.1 HARDWARE SCHEME ...............................................................................................................................61
18.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE–FRAME.............................................................62
18.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME ........................................................63
19. HDLC CONTROLLER FOR THE SA BITS OR DS0 ..................................................................65
19.1 GENERAL OVERVIEW ...............................................................................................................................65
19.2 HDLC STATUS REGISTERS ......................................................................................................................66
19.3 BASIC OPERATION DETAILS....................................................................................................................67
19.4 HDLC REGISTER DESCRIPTION ..............................................................................................................68
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