GL602USB データシートの表示（PDF） - Unspecified

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GL602USB

USB KEYBOARD MICROCONTROLLER

Unspecified 

4.2 USB FUNCTION REGISTERS

Address

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

Name

DEVCTL

EVTFLG

DEVADR

RXCTL0

TXCTL0

TXCTL123

FFDAT0

FFDAT123

DRVSEL

SENSE

FFRST

MODESEL

Reserved

EPSEL

SERCTL

SERDAT

Table 4-1 USB Function Register Summary

Function

Device control register

Event flag register

USB device address register

Endpoint 0 receive control register

Endpoint 0 transmit control register

Endpoint 1/2/3 transmit control register

Endpoint 0 FIFO data port

Endpoint 1/2/3 FIFO data port

Key matrix drive pin control register

Key matrix sense register

FIFO reset register

USB mode select register

Endpoint select register

PS/2 mouse port control register

PS/2 mouse port data register

DEVCTL (Address 10h, Device control register)

R/W[1]

R/W

R/W

R/W

R/W

R/W

R/W

EP3STL EP2STL EP1STL EP0STL WAKE WKDIS PWRDN

EP3STL: Endpoint 3 stall bit

1: Endpoint 3 will respond with a STALL to a valid transaction

0: Endpoint 3 will not respond with a STALL to a valid transaction

EP2STL: Endpoint 2 stall bit

1: Endpoint 2 will respond with a STALL to a valid transaction

0: Endpoint 2 will not respond with a STALL to a valid transaction

EP1STL: Endpoint 1 stall bit

1: Endpoint 1 will respond with a STALL to a valid transaction

0: Endpoint 1 will not respond with a STALL to a valid transaction

EP0STL: Endpoint 0 stall bit

1: Endpoint 0 will respond with a STALL to a valid transaction.

0: Endpoint 0 will not respond with a STALL to a valid transaction

WAKE: Wake-up bit

1: Set this bit to wake up host controller by placing USB bus into K state

0: Clear this bit to force USB bus leave K state

WKDIS: Wake-up disable bit

1: Disable remote wake-up capability

0: Enable remote wake-up capability

PWRDN: Power-down mode bit

1: Entering power-down mode

If USB suspend is detected, firmware should set this bit to enter power-down mode. In power-down mode,

6MHz crystal clock will be stopped. Hardware will automatically clear PWRDN bit upon hardware reset,

USB D+/D- toggle, SENSE1~SENSE8 at logic ‘0’, or Port 1.1 at logic ‘0’.

Value on POR: “0 0 0 0 0 0 0 0”

Note 1: “R/W” means readable and writable bit

EVTFLG (Address 11h, Event flag register)

R/W1C[1] R/W1C

R/W1C

R/W1C

WAKEUP RESUME SUSPD EP3TX

Revision 1.6

R/W1C

EP2TX

-11-

R/W1C

EP1TX

R/W1C

EP0TX

R/W1C

EP0RX

02/28/2000

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