HSP50216(2000) データシートの表示（PDF） - Intersil

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HSP50216
(Rev.:2000)

Four-Channel Programmable Digital DownConverter

Intersil 

Filter Compute Engine

HSP50216

The filter compute engine is a dual multiply-accumulator

(MAC) data path with a microcoded FIR sequencer. The filter

compute engine can implement a single FIR or a set of

filters. For example, the filter chain could include two

halfband filters, a shaping (matched) filter and a resampling

filter. The following filter types are currently supported by the

architecture and microcode:

• even symmetric w/ even # of taps decimation filters

• even symmetric w/ odd # of taps decimation filters

(including HBFs)

• odd symmetric w/ even # of taps decimation filters

• odd symmetric w/ odd # of taps decimation filters

• asymmetric decimation filters

• complex filters

• interpolation filters (up to interpolate by 4)

• interpolation halfband filters

• resampling filters (under NCO control)

• fixed resampling ratio filter (within the available number

of coefficients)

• quadrature to real filtering (w/ fs/4 up conversion)

The input to the filter compute engine comes from one of

three sources - a CIC filter output (which can also be another

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backend section), the output of the filter compute engine (fed

back to the input) or the magnitude and dφ/dt fed back from

the cartesian-to-polar coordinate converter.

The number and size of the filters in the chain is limited by

the number of clock cycles available and by the data and

coefficient RAM/ROM resources. The data RAM is 384

words (I/Q pairs) deep. The data addressing is modulo in

power-of-2 blocks, so the maximum filter size is 256. The

block size and the block starting memory address for each

filter is programmable so that the available memory can be

used efficiently. The coefficient RAM is 192 words deep. It is

half the size of the data memory because filter coefficients

are typically symmetric. ROMs are provided with halfband

filter coefficients, resampling filter coefficients, and

constants. The filter compute engine exploits symmetry

where possible so that each MAC can compute two filter

taps per clock, by doing a pre-add before multiplying. In the

case of halfband filters, the zero-valued coefficients are

skipped for extra efficiency. There is an overhead of one

clock cycle per input sample for each filter in the chain (for

writing the data into the data RAM) and (except in special

cases) a two clock cycle overhead for the entire chain for

program flow control instructions.

The output of the filter compute engine is routed through a

FIFO in the main output path. The FIFO is provided to more

evenly space the FIR outputs when they are produced in

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