HSP50216(2000) データシートの表示（PDF） - Intersil
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HSP50216 Datasheet PDF : 53 Pages
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HSP50216
The HSP50216 is programmed through a 16-bit
microprocessor interface. The output data can also be read
via the microprocessor interface for all channels that are
synchronized. The HSP50216 is specified to operate to a
Input Select/Format Block
maximum clock rate of 70MSPS over the industrial
temperature range (-40oC to 85oC). The power supply
voltage range is 3.3V ± 0.15V. The I/Os are not 5V tolerant.
Each front end block and the level detector block contains an
input select/format block. A functional block diagram is
provided in the above figure. The input source can be any of
the four parallel input busses (see Microprocessor Interface
Section Table 1, IWA *000h) or a test register loaded via the
processor bus (see Microprocessor Interface Section Table
40, GWA F807h).
The input to the part can operate in a gated or interpolated
mode. Each input channel has an input enable (ENIx, x = A,
B, C or D). In the gated mode, one input sample is
processed per clock that the ENIx signal is asserted (low).
Processing is disabled when ENIx is high. The ENIx signal is
pipelined through the part to minimize delay (latency). In the
interpolated mode, the input is zeroed when the ENIx signal
is high, but processing inside the part continues. This mode
inserts zeros between the data samples, interpolating the
input data stream up to the clock rate. On reset, the part is
set to gated mode and the input enables are disabled. The
inputs are enabled by the first SYNCI signal.
The input section can select one channel from a multiplexed
data stream of up to 8 channels. The input enable is delayed
by 0 to 7 clock cycles to enable a selection register. The
register following the selection register is enabled by the
non-delayed input enable to realign the processing of the
6
channels. The one-clock-wide input enable must align with
the data for the first channel. The desired channel is then
selected by programming the delay. A delay of zero selects
the first channel, a delay of 1 selects the second, etc.
The parallel input busses are 16 bits wide. The input format
may be twos complement or offset binary format. A floating
point mode is also supported. The floating point modes and
the mapping of the parallel 16-bit input format is discussed
below.
Floating Point Input Mode Bit Mapping
The input bit weighting for fixed point is 20 (corresponding to
parallel input bus A, B, C or D bit 15) to 2-15 (corresponding
to parallel input bus A, B, C or D bit 0). For floating point
modes, the least significant 2 or 3 bits are used as exponent
bits (See Floating Point Input Mode Bit Mapping Tables). The
difference between the four floating point modes with three
exponent bits is where the exponent saturates.
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