HSP50216(2000) データシートの表示（PDF） - Intersil

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HSP50216
(Rev.:2000)

Four-Channel Programmable Digital DownConverter

Intersil 

HSP50216

factor can be from 0 to 31. The equation used to compute

the shift factor is:

Shift Factor = 45 - Ceiling(log2(RN)).

NOTE: With a CIC order of zero, the CIC shifter does not have

sufficient range to route more than 10 bits to the back end.

Back End Section

One back-end processing section is provided per channel.

Each back end section consists of a filter compute engine, a

FIFO for rate smoothing, an AGC and a cartesian-to-polar

coordinate conversion block. A block diagram showing the

major functional blocks and data routing is shown above.

The data input to the back end section is through the filter

compute engine. There are two other inputs to the filter

compute engine, they are a data recirculation path for

cascading filters and a magnitude and dφ/dt feedback path

for AM and FM filtering. There are seven outputs from each

back end processing section. These are I and Q directly out

of the filter compute engine (I2, Q2), I and Q passed through

the FIFO and AGC multipliers (I1, Q1), magnitude (MAG),

phase (or dφ/dt), and the AGC gain control value (GAIN).

The I2/Q2 outputs are used when cascading back end

stages. The routing of signals within the back end

processing section is controlled by the filter compute engine.

The routing information is embedded in the instruction bit

fields used to define the digital filter being implemented in

the filter compute engine.

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