HD74LV00AFPEL(2010) データシートの表示（PDF） - Renesas Electronics
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HD74LV00AFPEL Datasheet PDF : 11 Pages
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HD74LV00A
Quad. 2-input NAND Gates
REJ03D0225–0300Z
(Previous ADE-205-240A (Z))
Rev.3.00
May 20, 2004
Description
The HD74LV00A has four two-input NAND gates in a 14-pin package.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current
±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV00AFPEL
SOP–14 pin(JEITA) FP–14DAV
FP
EL (2,000 pcs/reel)
HD74LV00ARPEL
SOP–14 pin(JEDEC) FP–14DNV
RP
EL (2,500 pcs/reel)
HD74LV00ATELL
TSSOP–14 pin
TTP–14DV
T
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
A
B
H
H
L
X
X
L
Note: H: High level
L: Low level
X: Immaterial
Output Y
L
H
H
Rev.3.00, May 20, 2004, page 1 of 8
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