HD74LVC533TELL データシートの表示（PDF） - Renesas Electronics

部品番号

コンポーネント説明

メーカー

HD74LVC533TELL

Octal D-type Transparent Latches with 3-state Outputs

Renesas Electronics 

HD74LVC533

Octal D-type Transparent Latches with 3-state Outputs

REJ03D0356–0400Z

(Previous ADE-205-070B (Z))

Rev.4.00

Jul. 27, 2004

Description

The HD74LVC533 has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is

high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at

the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all

outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the

storage elements. Low voltage and high-speed operation is suitable at the battery drive product (note type personal

computer) and low power consumption extends the life of a battery for long time operation.

Features

• VCC = 2.0 V to 5.5 V

• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)

• High output current ±24 mA (@VCC = 3.0 V to 5.5 V)

• Ordering Information

Part Name

Package Type

Package Code

HD74LVC533FPEL

SOP–20 pin (JEITA) FP–20DAV

HD74LVC533TELL

TSSOP–20 pin

TTP–20DAV

Note: Please consult the sales office for the above package availability.

Package

Abbreviation

FP

T

Taping Abbreviation

(Quantity)

EL (2,000 pcs/reel)

ELL (2,000 pcs/reel)

Function Table

Inputs

G

LE

D

H

X

X

L

H

L

L

H

H

L

L

X

H: High level

L: Low level

X: Immaterial

Z: High impedance

Q0: Level of Q before the indicated steady input conditions were established.

Output Q

Z

H

L

Q0

Rev.4.00 Jul. 27, 2004 page 1 of 7

Share Link: