HEF4043BT,653(2016) データシートの表示（PDF） - NXP Semiconductors.
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HEF4043BT,653 Datasheet PDF : 13 Pages
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Nexperia
HEF4043B
Quad R/S latch with 3-state outputs
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD
Typical formula for PD (W)
where:
PD
dynamic power 5 V
PD = 1100 fi + (fo CL) VDD2
fi = input frequency in MHz;
dissipation
10 V
PD = 4400 fi + (fo CL) VDD2
fo = output frequency in MHz;
15 V
PD = 11400 fi + (fo CL) VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
(fo CL) = sum of the outputs.
12. Waveforms
WU
WI
9,
LQSXWQ6
9
90
W:
9,
LQSXWQ5
9
92+
RXWSXWQ4
92/
W3/+
90
W7/+
90
W:
W3+/
W7+/
DDL
Fig 4.
tr and tf are the input rise and fall times.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times.
Measurement points are given in Table 9 and test data is given in Table 10.
Input minimum set (nS) and reset (nR) pulse widths, inputs nS or nR to latch output (nQ) propagation
delay and nQ transition time
HEF4043B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 24 March 2016
© Nexperia B.V. 2017. All rights reserved
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