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HY27UF084G2B データシートの表示(PDF) - Hynix Semiconductor

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HY27UF084G2B
Hynix
Hynix Semiconductor Hynix
HY27UF084G2B Datasheet PDF : 51 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
NOTE:
1. L must be set to Low.
1
HY27UF(08/16)4G2B Series
4Gbit (512Mx8bit) NAND Flash
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
L(1)
L(1)
L(1)
L(1)
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
L(1)
L(1)
L(1)
L(1)
L(1)
L(1)
Table 3: Address Cycle Map(x8)
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
IO0
IO1
IO2
IO3
IO4
IO5
IO6
A0
A1
A2
A3
A4
A5
A6
A8
A9
A10
L(1)
L(1)
L(1)
L(1)
A11
A12
A13
A14
A15
A16
A17
A19
A20
A21
A22
A23
A24
A25
A27
A28
L(1)
L(1)
L(1)
L(1)
L(1)
Table 4: Address Cycle Map(x16)
NOTE:
1. L must be set to Low.
2. In case of x16, I/O8 ~ I/O15 are don’t care
IO7
A7
L(1)
A18
A26
L(1)
I/O8-
IO15
L(1)
L(1)
L(1)
L(1)
L(1)
FUNCTION
READ1
READ FOR COPY-BACK
READ ID
RESET
PAGE PROGRAM
COPY BACK PGM
MULTI PLANE PROGRAM
MULTI PLANE COPYBACK
PROGRAM
BLOCK ERASE
MULTI PLANE
BLOCK ERASE
READ STATUS REGISTER
RANDOM DATA INPUT
RANDOM DATA OUTPUT
READ CACHE (RANDOM)
READ CACHE (SEQUENTIAL)
READ CACHE END
READ EDC STATUS REGISTER
1st CYCLE
00h
00h
90h
FFh
80h
85h
80h
85h
60h
60h
70h
85h
05h
00h
31h
3Fh
7Bh
2nd CYCLE
30h
35h
-
-
10h
10h
11h
3rd CYCLE
-
-
-
-
-
-
81h
4th CYCLE
-
-
-
-
-
-
10h
Acceptable command
during busy
Yes
11h
81h
10h
D0h
-
-
60h
D0h
-
-
-
-
Yes
-
-
-
E0h
-
-
31h
-
-
-
-
-
-
-
-
-
-
-
Table 5: Command Set
Rev 0.4 / Jan. 2008
8

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