HYM328020GD-50 データシートの表示（PDF） - Siemens AG

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HYM328020GD-50

8M × 32-Bit Dynamic RAM Module SMALL OUTLINE MEMORY MODULE

Siemens AG 

8M × 32-Bit Dynamic RAM Module

SMALL OUTLINE MEMORY MODULE

HYM 328020GD-50/-60

Preliminary Information

• 8 388 608 words by 32-bit organization

• Fast access and cycle time

50 ns access time

95 ns cycle time (-50 version)

60 ns access time

110 ns cycle time (-60 version)

• Fast page mode capability with

35 ns cycle time (-50 version)

40 ns cycle time (-60 version)

• Single + 3.3 V (± 0.3 V) supply

• Low power dissipation

max. 2016 mW active (-50 version)

max. 1728 mW active (-60 version)

LVCMOS– 3.6 mW standby

LVTTL – 28.8 mW standby

• CAS-before-RAS refresh, RAS-only-refresh, Self Refresh

• 4 decoupling capacitors mounted on substrate

• All inputs, outputs and clock fully TTL compatible

• 72 pin, dual read-out, two bank, Small Outline DIMM Module

• Utilizes four 4M × 16 -DRAMs (HYB 3165160T)

• 4096 refresh cycles / 64 ms

• Gold contact pad

Semiconductor Group

195

11.94

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