Q67100-Q2182 データシートの表示（PDF） - Siemens AG

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Q67100-Q2182

3.3V 2M × 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module

Siemens AG 

HYM 64(72)V2005GU-50/-60

2M x 64/72 DRAM Module

AC Characteristics (contd’ ) 5)6)

TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

-50

-60

min. max. min. max.

Hyper Page Mode (EDO) Read-modify-Write Cycle

Hyper page mode (EDO) read-write

tPRWC

58

–

68

–

ns

cycle time

CAS precharge to WE

tCPWD 41

–

49

–

ns

16E

Note

CAS-before-RAS Refresh Cycle

CAS setup time

tCSR

10

–

10

–

ns

CAS hold time

tCHR

10

–

10

–

ns

RAS to CAS precharge time

tRPC

5

–

5

–

ns

Write to RAS precharge time

tWRP

10

–

10

–

ns

Write hold time referenced to RAS

tWRH

10

–

10

–

ns

Capacitance

TA = 0 to 70 °C; VCC = 3.3 V ± 0.3 V; f = 1 MHz

Parameter

Input Capacitance (A0 to A9)

Input Capacitance (RAS0, RAS2)

Input Capacitance (CAS0-CAS7)

Input Capacitance (WE0,WE2,OE0,OE2)

I/O Capacitance (DQ0-DQ63,CB0-CB8)

Input Capacitance (SCL, SA0-2)

Input/Output Capacitance (SDA)

Symbol

CI1

CI2

CI3

CI4

CIO1

Cs

Cs

Limit Values

min.

max.

–

55

–

50

–

10

–

50

–

11

–

8

–

10

Unit

pF

pF

pF

pF

pF

pF

pF

Semiconductor Group

11

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