UAA3545HL データシートの表示（PDF） - Philips Electronics

部品番号

コンポーネント説明

メーカー

UAA3545HL

Fully integrated DECT transceiver

Philips Electronics 

Philips Semiconductors

Fully integrated DECT transceiver

Product specification

UAA3545

FUNCTIONAL DESCRIPTION

Transmit chain

VCO AND PRESCALER

The fully integrated VCO operates at a multiple of the

DECT frequency. It is supplied by an on-chip voltage

regulator to minimize frequency disturbances due to

supply voltage variations. The VCO signal is fed into a

prescaler. A large difference between transmitted and

VCO frequencies reduces transmitter-oscillator coupling

problems.

The output of the prescaler drives the synthesizer main

divider. The divider output can also be switched to either

the TX preamplifier or the RX LO output buffer. The high

isolation obtained from the prescaler ensures very small

frequency changes when turning-on the TX preamplifier or

the RX section. In TX mode, the oscillator can be

modulated directly with GFSK-filtered data at pin VMOD.

TX PREAMPLIFIER

The TX preamplifier amplifies the RF signal to a level of

3 dBm (typical) which is suitable for use with Philips

Semiconductors DECT power amplifiers.

Synthesizer

MAIN DIVIDER

The main divider is clocked by the RF signal from the

prescaler at frequencies from 1880 to 1930 MHz. Any

main divider ratio from 2176 to 2303 inclusive can be

programmed.

REFERENCE DIVIDER

The reference divider is clocked by the signal at pin XTAL.

The circuit operates with levels from 1.2 to 1.8 V (p-p) at a

frequency of 3.456 MHz. By programming the ‘REFD’ bits

of the serial input register (see Table 1) the reference

frequency can be set for 6.912, 10.368 or 13.864 MHz.

PHASE COMPARATOR

The phase comparator is driven by the output of the main

and reference dividers. It produces current pulses at

pin CP/VCOtune, the pulse duration being the difference in

arrival time of current pulse edges from the two dividers.

If the main divider edge arrives first, pin CP sinks current.

If the reference divider edge arrives first, pin CP sources

current. The DC value of the charge-pump current is

defined by an internal resistor. Additional circuitry is

included to ensure the gain of the phase detector remains

linear even for small phase errors.

Serial programming bus

A simple 3-line unidirectional serial bus is used to

program the circuit. The three lines are data (S_DATA),

serial clock (S_CLK) and serial bus enable (S_EN). Data

sent to the device are loaded in bursts framed by S_EN.

Programming clock edges and their appropriate data bits

are ignored until S_EN goes active (LOW). The

programmed information is read directly by the main

divider when S_EN returns to HIGH. S_DATA and S_EN

change value on the falling edge of S_CLK.

During synthesizer operation, S_EN should be held

HIGH. Only the last 24 bits clocked into the device are

retained within the serial register. Additional leading bits

are ignored and no check is made on the number of clock

pulses. The data format is shown in Table 1. The first bit

entered is b23, the last bit is b0. For the main divider ratio,

the first bit (b5) is the Most Significant Bit (MSB).

The serial bus enable (S_EN) must be LOW to capture

new programming data and must be HIGH to switch on the

synthesizer.

2001 Sep 06

7

Share Link: