UAA3545HL データシートの表示（PDF） - Philips Electronics
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UAA3545HL Datasheet PDF : 28 Pages
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Philips Semiconductors
Fully integrated DECT transceiver
Product specification
UAA3545
Programming
Table 1 Serial interface register
first in
b23 to b20
TEST(2)
b19
SLIC(3)
REGISTER BIT ALLOCATION
b18, b17 b16 to b10
b9
REFD(4) TEST(2) SPWR(5)
b8
PLL(6)
b7
NEW(5)
b6
TRX
last in
b5 to b0(1)
MAIN DIVIDER(7)
Notes
1. Bit b5 is the MSB of the main divider coefficient; this comprises bits b5, b4, b3, b2, b1, b0 and b6 (TRX).
2. Test bits b23, b22, b21, b20, b16, b15, b14, b13, b12, b11, b10 must always be programmed to 0.
3. Bit ‘SLIC’ = 1 forces the internal slicer on. In this mode, pin DATAM is connected to an external capacitor. Together
with an internal 1 kΩ resistor, it defines the low pass time constant for the slicer threshold voltage. When the
bit ‘SLIC’ = 0, the pin RDATAP is connected directly to the demodulator output and delivers an analog signal.
Pin DATAM also reflects the demodulator voltage without the internal 1 kΩ resistor when the SLCCTR pin is HIGH.
4. REFD sets the reference divider ratio to 4, 8, 12 or 16 (corresponding respectively to a reference input frequency of
3.456, 6.912, 10.368 or 13.824 MHz) (see Table 4).
5. Bits ‘NEW’, and ‘SPWR’ select the operating mode (see Table 3).
6. Bit ‘PLL’ = 1 forces the PLL to remain on when the VCO is on.
7. The main divider ratio is equal to 2176 + the programmed value (see Table 2).
Table 2 Main divider programming
BIT
b5
b4
b3
b2
b1
Binary equivalent of n
0
0
0
0
0
0
1
0
1
1
b0 b6 (TRX)
MAIN DIVIDER
RATIO
SYNTHESIZED
FREQUENCY (MHz)
2176 + n
0.864 × (2176 + n)
0
0
2 176
1 880.064
1
1
2 223
1 920.672
Table 3 Operating mode selection
BIT
b9 (SPWR)
0
0
1
1
b7 (NEW)
0
1
0
1
OPERATING MODE
normal mode (mode 1)
reduced signal mode (mode 2)
do not use
advanced signal mode (mode 3)
Table 4 Reference divider ratio programming
BIT
b18
b17
0
0
0
1
1
0
1
1
REFERENCE DIVIDER RATIO
4
16
8
12
REFERENCE INPUT FREQUENCY
3.456 MHz
13.824 MHz
6.912 MHz
10.368 MHz
2001 Sep 06
9
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