IPU12N03LBG データシートの表示（PDF） - Infineon Technologies

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IPU12N03LBG

OptiMOS®2 Power-Transistor

Infineon Technologies 

IPD12N03LB G

IPU12N03LB G

IPS12N03LB G

IPF12N03LB G

Parameter

Symbol Conditions

min.

Values

typ.

Unit

max.

Thermal characteristics

Thermal resistance, junction - case R thJC

-

SMD version, device on PCB

R thJA minimal footprint

-

6 cm2 cooling area5)

-

-

2.9 K/W

-

75

-

50

Electrical characteristics, at T j=25 °C, unless otherwise specified

Static characteristics

Drain-source breakdown voltage

Gate threshold voltage

Zero gate voltage drain current

Gate-source leakage current

Drain-source on-state resistance

Gate resistance

Transconductance

V (BR)DSS V GS=0 V, I D=1 mA

30

V GS(th) V DS=V GS, I D=20 µA

1.2

I DSS

V DS=30 V, V GS=0 V,

T j=25 °C

-

V DS=30 V, V GS=0 V,

T j=125 °C

-

I GSS

V GS=20 V, V DS=0 V

-

R DS(on) V GS=4.5 V, I D=20 A

-

V GS=4.5 V, I D=20 A,

-

SMD version

V GS=10 V, I D=30 A

-

V GS=10 V, I D=30 A,

-

SMD version

RG

-

g fs

|V DS|>2|I D|R DS(on)max,

I D=30 A

21

-

-V

1.6

2

0.1

1 µA

10

100

10

100 nA

14.3 17.9 mΩ

14.1 17.7

9.8

11.8

9.6

11.6

1

-Ω

43

-S

1) J-STD20 and JESD22

1) Current is limited by bondwire; with an R thJC=2.9 K/W the chip is able to carry 50 A.

3) See figure 3

4) T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V

5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain

connection. PCB is vertical in still air.

Rev. 1.5

page 2

2006-05-15

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