LS7266R1 データシートの表示（PDF） - LSI Corporation

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LS7266R1

24-BIT DUAL-AXIS QUADRATURE COUNTER

LSI Corporation  

INPUTS/OUTPUTS

X-AXIS I/Os:

XA (Pin 20)

XB (Pin 21)

XLCNTR/XLOL

(Pin 19)

X-axis count input A

X-axis count input B

Either quadrature encoded clocks or non-quadrature clocks can be applied

to XA and XB. In quadrature mode XA and XB are digitally filtered and decoded

for UP/DN clock. In non-quadrature mode, the filter and the decoder circuits are

by-passed. Also, in non-quadrature mode XA serves as the count input and XB

as the UP/DOWN direction control input, with XB = 1 selecting Up Count mode

and XB = 0, selecting Down Count mode.

X-axis programmable input, to operate as either direct load XCNTR or direct load XOL or synchronous

load XCNTR or synchronous load XOL. The synchronous load mode is intended for interfacing with

the encoder Index output in quadrature clock mode. In direct load mode, a logic low level is the active

level at this input. In synchronous load mode the active level can be programmed to be either logic

low or logic high. Both quarter-cycle and half-cycle Index signals are supported by this input in the in-

dexed Load mode. The synchronous function must be disabled in non-quadrature count mode (See

description of IDR on P. 4)

XRCNTR/XABG

(Pin 18)

X-axis programmable input to operate either as direct reset XCNTR or count enable/disable gate or

synchronous reset XCNTR. The synchronous reset XCNTR mode is intended for interfacing with the

encoder Index output in quadrature clock mode. In direct reset XCNTR mode, a logic low level is the

active level at this input whereas in synchronous reset XCNTR mode the active level can be pro-

grammed to be either a logic low or a logic high. Both quarter-cycle and half-cycle index signals are

supported by this input in the indexed reset CNTR mode. The synchronous function must be disabled

in non-quadrature count mode (See description of IDR on P. 4). In count enable/disable mode, a logic

high at this input enables the counter and a logic low level disables the counter.

XFLG1 (Pin 22) X-axis programmable output to operate either as XCARRY (Active low), or XCOMPARE (generated

when XPR=XCNTR; Active low), or XIDX (XFLAG bit 6) or XCARRY/XBORROW (Active low).

XFLG2 (Pin 23) X-axis programmable output to operate as either XBORROW (Active low) or XU/D (XFLAG bit 5)

or XE (XFLAG bit 4).

Y-AXIS I/Os:

All the X-axis inputs/outputs are duplicated for the Y-axis with similar functionalities.

YA (Pin 25)

YB (Pin 24)

YLCNTR/YLOL (Pin 1)

YRCNTR/YABG (Pin 28)

YFLG1 (Pin 27)

YFLG2 (Pin 26)

COMMON I/Os:

WR (Pin 14)

Write input. Control/data bytes are written at the trailing edge of low level pulse applied to this input.

RD (Pin 16)

Read input. A low level applied to this input enables the FLAGs and OLs to be read on the data bus.

CS (Pin 15)

Chip select input. A low level applied to this input enables the chip for Read and Write.

C/D (Pin 13)

Control/Data input. This input selects between a control register or a data register for Read/Write.

When low, a data register is selected. When high, a control register is selected.

D0-D7

(Pins 4-11)

Data Bus input/output. The 8-bit three-state data bus is the I/O port through which all data transfers

take place between the LS7266R1 and the host processor.

FCK (Pin 2)

Filter clock input in quadrature mode. The FCK is divided down internally by two 8-bit programmable

prescalers, one for each channel.

X/Y (Pin 17)

Selects between X and Y axes for Read or Write. X/Y = 0 selects X-axis and X/Y = 1 selects Y-axis.

X/Y is overridden by D7 =1 in Control Write Mode (C/D = 1).

VDD (Pin 3)

+5VDC

VSS (Pin 12)

7266R1-011498-7

GND

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