LT3710 データシートの表示（PDF） - Linear Technology

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LT3710

Secondary Side Synchronous Post Regulator

Linear Technology 

LT3710

APPLICATIO S I FOR ATIO

Output N-Channel MOSFET Drivers

The LT3710 employs high speed N-channel MOSFET

synchronous drivers to achieve high system efficiency.

GBIAS is the 8V regulator output to bias and supply the

drivers and should be properly bypassed with a low ESR

capacitor to ground plane. A Schottky catch diode is

required on the switch node.

Light Load Operation

If the BGS pin is grounded, the LT3710 stays in continuous

mode independent of load condition except in soft-start

operation (see Soft-Start section). If the BGS pin is left

open, under light load and VRS1 drops below 8mV, BGATE

will be turned off(see comparator CA2 of Block Diagram)

and the LT3710 goes into discontinous mode operation.

Current Limit

Current limit is set by the 70mV threshold across CL+ and

CL–, the inputs of the amplifier CA1. By connecting an

external resistor RS1(see Block Diagram), the current

limit is set for 70mV/RS1. R6 and C6 stablize the current

limit loop. If current limit is not used, both CL+ and CL–

should be grounded and the BGS pin should also be

grounded to disable comparator CA2.

Soft-Start and Shutdown

During soft-start, VSS is the reference voltage that controls

the output voltage and the output ramps up following VSS.

The effective range of VSS is from 0V to VREF. The typical

time for the output to reach the programmed level is

(C • 0.8V)/10µA.

During start up, BGATE will stay off until VSS gets up to

1.6V. This prevents the bottom MOSFET from turning on

if the output is precharged.

To shut down the LT3710, the SS pin should be pulled

below 50mV by a VN2222 type N-channel transistor. Note

that during shutdown BGATE will be locked off when VSS

drops below 0.6V. This prevents the bottom MOSFET from

discharging the output, which would cause the output to

undershoot below ground.

Layout Considerations

For maximum efficiency, the switching rise and fall times

are less than 20ns. To prevent radiation, the power

MOSFETs, SW pin and input bypass capacitor leads should

be kept as short as possible. A ground plane should be

used under the switching circuitry to prevent interplane

coupling and to act as a thermal spreading path. Note that

the bottom metal of the package is the heat sink, as well as

the IC signal ground, and must be soldered to the ground

plane.

Output Voltage Programming

The feedback reference voltage is 0.8V. The output voltage

can be easily programmed by the resistor divider, R3 and

R4, as shown in the Block Diagram.

VOUT2

=

0.8 • 1+

R3

R4



Filtering on the SYNC Input

It is necessary to add RC filtering on the SYNC input of the

LT3710 to eliminate the negative glitch at the turn on of the

top MOSFET. When the top MOSFET M1 turns on, the

transformer secondary current instantly changes from the

original first output inductor current to the sum of two

output inductor currents. The high di/dt on the trans-

former leakage inductance causes the transformer sec-

ondary voltage VS to drop for a short interval. If the leakage

inductance is large enough, the VS dip will be lower than

the synchronization threshold (about 2.5V), falsely trig-

gering the synchronization. The top MOSFET is turned off

immediately. As a result, the output voltage will not be

regulated properly.

A filter circuit is needed to ensure proper operation. A

small RC filter with RS = 10k and CS = 10pF are typical.

3710f

8

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