LTC4150 データシートの表示（PDF） - Linear Technology

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LTC4150

Coulomb Counter/Battery Gas Gauge

Linear Technology 

LTC4150

APPLICATIONS INFORMATION

INT, POL and CLR

INT asserts low each time the LTC4150 measures a unit

of charge. At the same time, POL is latched to indicate

the polarity of the charge unit. The integrator and counter

continue running, so the microcontroller must service and

clear the interrupt before another unit of charge accumu-

lates. Otherwise, one measurement will be lost. The time

available between interrupts is the reciprocal of

Equation 2:

Time per INT Assertion =

1

GVF •⏐VSENSE⏐

(9)

At 50mV full scale, the minimum time available is 596ms.

To be conservative and accommodate for small, unex-

pected excursions above the 50mV sense voltage limit, the

microcontroller should process the interrupt and polarity

information and clear INT within 500ms.

Toggling CLR low for at least 20μs resets INT high and

unlatches POL. Since the LTC4150’s integrator and counter

operate independently of the INT and POL latches, no

charge information is lost during the latched period or

while CLR is low. Charge/discharge information contin-

ues to accumulate during those intervals and accuracy

is unaffected.

Once cleared, INT idles in a high state and POL indicates

real-time polarity of the battery current. POL high indicates

charge flowing into the battery and low indicates charge

flowing out. Indication of a polarity change requires at

least:

tPOL

=

GVF

•

2

1024 •⏐VSENSE⏐

(10)

where VSENSE is the smallest sense voltage magnitude

before and after the polarity change.

Open-drain outputs POL and INT can sink IOL = 1.6mA

at VOL = 0.5V. The minimum pull-up resistance for these

pins should be:

RL > (VCC – 0.5)/1.6mA

(11)

where VCC is the logic supply voltage. Because speed isn’t

an issue, pull-up resistors of 10k or higher are adequate.

Interfacing to INT, POL, CLR and SHDN

The LTC4150 operates directly from the battery, while in

most cases the microcontroller supply comes from some

separate, regulated source. This poses no problem for INT

and POL because they are open-drain outputs and can

be pulled up to any voltage 9V or less, regardless of the

voltage applied to the LTC4150’s VDD.

CLR and SHDN inputs require special attention. To drive

them, the microcontroller or external logic must generate

a minimum logic high level of 1.9V. The maximum input

level for these pins is VDD + 0.3V. If the microcontroller’s

supply is more than this, resistive dividers must be used

on CLR and SHDN. The schematic in Figure 6 shows an

application with INT driving CLR and microcontroller VCC

> VDD. The resistive dividers on CLR and SHDN keep the

voltages at these pins within the LTC4150’s VDD range.

Choose R2 and R1 so that:

(R1 + R2) ≥ 50RL

(12)

1.9V

≤

R1

R1+ R2

VCC

≤

VDD

(Minimum)

(13)

Equation 13 also applies to the selection of R3 and R4.

The minimum VDD is the lowest supply to the LTC4150

when the battery powering it is at its lowest discharged

voltage.

When the battery is removed in any application, the CLR

and SHDN inputs are unpredictable. INT and POL outputs

may be erratic and should be ignored until after the bat-

tery is replaced.

If desired, the simple logic of Figure 4 may be used to

derive separate charge and discharge pulse trains from

INT and POL.

INT

CHARGE

CLR

LTC4150

DISCHARGE

POL

4150 F04

Figure 4. Unravelling Polarity—

Separate Charge and Discharge Outputs

4150fc

9

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