LY6220488UL-55LLI データシートの表示（PDF） - Lyontek Inc.

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LY6220488UL-55LLI

2048K X 8 BIT LOW POWER CMOS SRAM

Lyontek Inc. 

®

Rev. 0.3

LY6220488

2048K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS

PARAMETER

VCC for Data Retention

Data Retention Current

Chip Disable to Data

Retention Time

Recovery Time

tRC* = Read Cycle Time

SYMBOL TEST CONDITION

MIN.

VDR CE# ≧ VCC - 0.2V or CE2 ≦0.2V

1.5

VCC = 1.5V

-LL -

IDR CE# ≧VCC - 0.2V or CE2 ≦0.2V -LLE -

Other pins at 0.2V or VCC - 0.2V -LLI -

tCDR

See Data Retention

Waveforms (below)

0

tR

tRC*

TYP.

-

8

8

8

-

-

MAX.

5.5

50

60

80

UNIT

V

µA

µA

µA

-

ns

-

ns

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) (CE# controlled)

Vcc

CE#

Vcc(min.)

tCDR

VIH

VDR ≧ 1.5V

CE# ≧ Vcc-0.2V

Vcc(min.)

tR

VIH

Low Vcc Data Retention Waveform (2) (CE2 controlled)

Vcc

CE2

Vcc(min.)

tCDR

VIL

VDR ≧ 1.5V

CE2 ≦ 0.2V

Vcc(min.)

tR

VIL

Lyontek Inc. reserves the rights to change the specifications and products without notice.

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

8

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