M12L128324A-7TG データシートの表示（PDF） - [Elite Semiconductor Memory Technology Inc.
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M12L128324A-7TG Datasheet PDF : 1 Pages
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ESMT
SDRAM
FEATURES
y JEDEC standard 3.3V power supply
y LVTTL compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs
- CAS Latency (1, 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
y All inputs are sampled at the positive going edge of the
system clock
y DQM for masking
y Auto & self refresh
y 64ms refresh period (4K cycle)
M12L128324A
1M x 32 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
Product No. MAX FREQ. PACKAGE COMMENTS
M12L128324A-6TG 166MHz 86 TSOPII Pb-free
M12L128324A-7TG 143MHz 86 TSOPII Pb-free
M12L128324A-6BG 166MHz 90 FBGA Pb-free
M12L128324A-7BG 143MHz 90 FBGA Pb-free
GENERAL DESCRIPTION
The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.4
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