M29DW323DB70N1 データシートの表示（PDF） - Numonyx -> Micron

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M29DW323DB70N1

32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block) 3V Supply Flash Memory

Numonyx -> Micron 

M29DW323DT, M29DW323DB

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram, and Table

1., Signal Names, for a brief overview of the sig-

nals connected to this device.

Address Inputs (A0-A20). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the Program/Erase Con-

troller.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation. During Bus Write

operations they represent the commands sent to

the Command Interface of the Program/Erase

Controller.

Data Inputs/Outputs (DQ8-DQ14). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation when BYTE is High,

VIH. When BYTE is Low, VIL, these pins are not

used and are high impedance. During Bus Write

operations the Command Register does not use

these bits. When reading the Status Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A–1).

When BYTE is High, VIH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, VIL, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of the ad-

dressed Word, DQ15A–1 High will select the MSB.

Throughout the text consider references to the

Data Input/Output to include this pin when BYTE is

High and references to the Address Inputs to in-

clude this pin when BYTE is Low except when

stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

VPP/Write Protect (VPP/WP). The VPP/Write

Protect pin provides two functions. The VPP func-

tion allows the memory to use an external high

voltage power supply to reduce the time required

for Program operations. This is achieved by by-

passing the unlock cycles and/or using the Dou-

ble Word or Quadruple Byte Program commands.

The Write Protect function provides a hardware

method of protecting the two outermost boot

blocks.

When VPP/Write Protect is Low, VIL, the memory

protects the two outermost boot blocks; Program

and Erase operations in these blocks are ignored

while VPP/Write Protect is Low, even when RP is

at VID.

When VPP/Write Protect is High, VIH, the memory

reverts to the previous protection status of the two

outermost boot blocks. Program and Erase oper-

ations can now modify the data in these blocks un-

less the blocks are protected using Block

Protection.

When VPP/Write Protect is raised to VPP the mem-

ory automatically enters the Unlock Bypass mode.

When VPP/Write Protect returns to VIH or VIL nor-

mal operation resumes. During Unlock Bypass

Program operations the memory draws IPP from

the pin to supply the programming circuits. See the

description of the Unlock Bypass command in the

Command Interface section. The transitions from

VIH to VPP and from VPP to VIH must be slower

than tVHVPP, see Figure 17.

Never raise VPP/Write Protect to VPP from any

mode except Read mode, otherwise the memory

may be left in an indeterminate state.

The VPP/Write Protect pin must not be left floating

or unconnected or the device may become unreli-

able. A 0.1µF capacitor should be connected be-

tween the VPP/Write Protect pin and the VSS

Ground pin to decouple the current surges from

the power supply. The PCB track widths must be

sufficient to carry the currents required during

Unlock Bypass Program, IPP.

Reset/Block Temporary Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to the memory or

to temporarily unprotect all Blocks that have been

protected.

Note that if VPP/WP is at VIL, then the two outer-

most boot blocks will remain protected even if RP

is at VID.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High, VIH, the memory will be ready for Bus

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/Busy

Output section, Table 19. and Figure 16., Reset/

Block Temporary Unprotect AC Waveforms, for

more details.

Holding RP at VID will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a Program or Erase

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