M2S28D20ATP データシートの表示（PDF） - MITSUBISHI ELECTRIC
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M2S28D20ATP Datasheet PDF : 36 Pages
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DDR SDRAM (Rev.0.1)
Jun,'00 Preliminary
PIN FUNCTION
SYMBOL
TYPE
CLK, /CLK
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-11
Input
BA0,1
DQ0-15(x16),
DQ0-7(x8),
DQ0-3(x4),
Input
Input / Output
DQS
Input / Output
/QFC
Output
DM
Input
Vdd, Vss
VddQ, VssQ
Vref
Power Supply
Power Supply
Input
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CLK and negative edge of /CLK. Output (read) data is referenced to
the crossings of CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal
clock for the following cycle is ceased. CKE is also used to select auto /
self refresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11. The Column Address is
specified by A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to
indicate precharge option. When A10 is high at a read / write
command, an auto precharge is performed. When A10 is high at a
precharge command, all banks are precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-
aligned with read data, centered in write data. Used to capture write
data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
FET Control: Optional. Output during every Read and Write access. Can
be used to control isolation switches on modules. Open drain output.
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-
DQ7; UDM corresponds to the data on DQ8-DQ15.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
SSTL_2 reference voltage.
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