M5M51R16AWG-10H データシートの表示（PDF） - MITSUBISHI ELECTRIC

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M5M51R16AWG-10H

1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM

MITSUBISHI ELECTRIC  

MITSUBISHI LSIs

M5M51R16AWG -10L, -12L, -15L,

-10H, -12H, -15H

1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM

FUNCTION

The operation mode of the M5M51R16A series are

determined by a combination of the device control

inputs S, W, OE, BC1 and BC2. Each mode is

summarized in the function table.

A write cycle is executed whenever the low level W

overlaps with the low level BC1 and/or BC2 and the

low level S. The address must be set up before the

write cycle and must be stable during the entire cycle.

The data is latched into a cell on the trailing edge of

W, BC1, BC2 or S, whichever occurs first, requiring

the set-up and hold time relative to these edge to be

maintained. The output enable input OE directly

controls the output stage. Setting the OE at a high

level, the output stage is in a high-impedance state,

and the data bus contention problem in the write cycle

is eliminated.

A read cycle is executed by setting W at a high level

and OE at a low level while BC1 and/or BC2 and S

are in an active state. (BC1 and/or BC2=L, S=L)

When setting BC1 at a high level and the other pins

are in an active state, upper-Byte are in a selectable

mode in which both reading and writing are enabled,

and lower -Byte are in a non-selectable mode. And

when setting BC2 at a high level and the other pins

are in an active state, lower-Byte are in a selectable

mode in which both reading and writing are enabled,

and upper -Byte are in a non-selectable mode.

When setting BC1 and BC2 at a high level or S at

a high level, the chips are in a non-selectable mode in

which both reading and writing are disabled.

In this mode, the output stage is in a high-impedance

state, allowing OR -tie with other chips and memory

expansion by BC1, BC2 and S. S, BC1 and BC2

control the power down feature. When S, BC1 and

BC2 go high, the power supply current is reduced as

low as the stand-by current which is specified as Icc3

or Icc4, and the memory data can be held at +1.0V

power supply, enabling battery back-up operation

during power-failure or power-down operation in the

non-selected mode.

FUNCTION TABLE

S W OE BC1 BC2

Mode

DQ1~8 DQ9~16 Icc

LHL L L

Word Read

Dout Dout Active

LHL

H

L

Upper-Byte Read

(Lower-Byte Non selection)

High-Z

Dout

Active

LHL L

LLX L

H Lower-Byte Read

(Upper-Byte Non selection)

L

Word Write

Dout

Din

High-Z

Din

Active

Active

LLX H L

Upper-Byte Write High-Z Din

(Lower-Byte Non selection)

Active

LLX L H

Lower-Byte Write

Din High-Z Active

(Upper-Byte Non selection)

L HH X X

Output disable

High-Z High-Z Active

XXX H H

Non selection

High-Z High-Z Stand-by

HXX X X

Non selection

High-Z High-Z Stand-by

(High-Z=High-impedance)

BLOCK DIAGRAM

A4 D4

A3 A4

A2 B4

A1 C4

A0 A5

A15 H5

A14 F4

A13 G4

A12 H4

ADDRESS

INPUTS

A8 H2

A9 F3

A10 G3

A11 H3

A7 B3

A5 C3

A6 A3

CHIP SELECT

INPUT S B5

WRITE CONTROL

INPUT

W

G5

OUTPUT

ENABLE

INPUT

OE A2

BYTE

CONTROL

INPUTS

BC2 B2

BC1 A1

65536 WORDS x16 BITS

( 512 ROWS

x 256 COLUMNS

x 8 BLOCKS )

CLOCK

GENERATOR

B6 DQ1

C5 DQ2

C6 DQ3

D5 DQ4

E5 DQ5

F6 DQ6

F5 DQ7

G6 DQ8

G1 DQ9

F2 DQ10

F1 DQ11

E2 DQ12

D2 DQ13

C1 DQ14

C2 DQ15

B1 DQ16

DATA

INPUTS/

OUTPUTS

D6 Vcc

E1 Vcc

E6 GND

(0V)

D1 GND

(0V)

E3 GND

(0V)

Aug.1. 1998

MITSUBISHI

ELECTRIC

2

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