M64285FP データシートの表示（PDF） - MITSUBISHI ELECTRIC

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M64285FP

CMOS Image Sensor (Image inputting systems for gaming devices, Toys, PC interface systems)

MITSUBISHI ELECTRIC  

Technical Data Sheet

MITSUBISHI

PRELIMINARY

MITSUBISHI CMOS Image Sensor

M64285FP

13. Operational Timing

13.1. Chip Reset • Register Set • Image Capture Start

The registers are set after resetting the chip. The timing chart below shows the operation up

to the image capture. RESET is done asynchronous with CLK. The input data, SIN, which

is used to set registers is inputted serially asynchronous with CLK and latched to the registers

by the LOAD signal. Detailed timing of SIN and LOAD is given in "13.2. Register Set".

After the contents of all registers have been decided, START is inputted in synchronous with

the rise of CLK. Then, the counter used for controlling purposes is reset to the initial value

which is specified by the register. Now, the image capture starts. If the period of LOAD or

START is longer than 2 CLKs, the valid timing is the first CLK rise for LOAD, and the last

CLK rise for START.

CLK

RESET

SIN

Add 0 Dat 0

Add 1 Dat 1

Add 2 Dat14

Add15 Dat15

LOAD

START

Reg 0

0000

Data 0

Reg 1

0000

Data 1

Reg 14

Reg 15

0000

1110

Data14

Data15

13.2. Register Set

The input data SIN is composed of 8 bits (x16). The leading 4 bits are the address and the

following 4 bits are data. The input data is transferred to a temporary register at the rising

edge of SCLK (asynchronous with CLK), and when LOAD goes "H", the contents of the

register become fixed at the rising edge of CLK.

SCLK

SIN

LOAD

A3 A2 A1 A0 D3 D2 D1 D0 A3 A2 A1 A0 D3 D2 D1 D0 A3 A2 A1 A0

Address 0

Data 0

Address 1

Data 1

Address 2

CLK

Data 0 becomes Valid

Data 1 becomes Valid

( 14 / 26 )

Specifications and information herein are subject to change without notice.

02 / 05 / 01

Ver. 2.2E_01

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