M64898GP データシートの表示（PDF） - Renesas Electronics

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M64898GP

PLL Frequency Synthesizer with DC/DC Converter For PC

Renesas Electronics 

M64898GP

Pin Description

Pin

No. Symbol

1 fin

2 GND

3

VCC1

4

VCC2

5 BS4

6 BS3

7 BS2

8 BS1

9 VDC

10 lpk

Pin Name

Prescaler input

GND

Power supply voltage 1

Power supply voltage 2

Band switching outputs

DC/DC power supply voltage

Peak current detect

11 SWE

12 +B

13 Vtu

14 Vin

Switching output

Power supply voltage

Tuning output

Filter input

(charge pump output)

15 LD/ftest Lock detect/Test port

16 CONT

fREF Switch

17 CLOCK Clock input

18 DATA

Data input

19 ENABLE Enable input

20 Xin

This is connected to the crystal

oscillator.

Function

Input for the VCO frequency.

Ground to 0 V.

Power supply voltage terminal. 5.0 V ± 0.5 V

Power supply for band switching, VCC1 to 10 V

PNP open collector method is used.

When the band switching data is “H”, the output is ON.

When it is “L”, the output is OFF.

DC/DC power supply voltage terminal. 5.0 V ± 0.5V

When potential difference with VDC terminal becomes more

than 0.33 V by current limiting detector of DC/DC converter,

the listing rises with off.

DC/DC converter oscillator output.

Power supply voltage for tuning voltage.

This supplies the tuning voltage.

This is the output terminal for the LPF input and charge pump

output. When the phase of the programmable divider output

(f 1/N) is ahead compared to the reference frequency (fREF),

the “source” current state becomes active.

If it is behind, the “sink” current becomes active.

If the phases are the same, the high impedance state

becomes active.

Lock detector output. When loop of phase locked loop locked

it, it rise with “H” level in “L” level or unlock.

In control byte data input, the programmable freq. divider

output and reference freq.

output is selected by the test mode.

Set up reference frequency divider ratio.

In “L” level, set it up in 1/640 (19 Bit) in setting “opening” in

1/1024 (19 Bit) or 1/512 (18 Bit).

Data is read into the shift register when the clock signal falls.

Input for band SW and programmable freq. divider set up.

This normally at a “L”. When this is at “H”, data and clock

signals are received. Data is read into the latch when the

enable signal after the 18th signal of the clock signal falls or

when the 19th pulse of the clock signal falls.

4.0 MHz crystal oscillator connected.

Rev.2.00 Jun 14, 2006 page 4 of 13

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