MAX5712 データシートの表示（PDF） - Maxim Integrated

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MAX5712

Low-Power, 12-Bit, Rail to Rail Voltage-Output Serial DAC in SOT23

Maxim Integrated 

MAX5712

Low-Power, 12-Bit, Rail to Rail

Voltage-Output Serial DAC in SOT23

Detailed Description

The MAX5712 voltage output, 12-bit DAC, offers a full

12-bit performance in a small 6-pin SOT23 package.

The SOT23 footprint is less than 9mm2. The MAX5712

has less than 1LSB differential nonlinearity error, ensur-

ing monotonic performance. The device uses a simple

3-wire, SPI/QSPI/MICROWIRE and DSP-compatible seri-

al interface that operates up to 20MHz. The MAX5712

incorporates three shutdown modes, making it ideal for

low-power.

Analog Section

The MAX5712 consists of a resistor string, an output buf-

fer, and a POR circuit. Monotonic digital to analog conver-

sion is achieved using a resistor string architecture. Since

VDD is the reference for the MAX5712, the accuracy of

the DAC depends on the accuracy of VDD. The low bias

current of the MAX5712 allows its power to be supplied

by a voltage reference such as the MAX6030. The 12-bit

DAC code is binary-unipolar with 1LSB = VDD/4096.

Output Buffer

The DAC output buffer has a rail-to-rail output and is

capable of driving a 5kΩ resistive load in parallel with a

200pF capacitive load. With a capacitive load of 200pF,

the output buffer slews 0.5V/μs. With a 1/4FS to 3/4FS

output transition, the amplifier output settles to 1/2LSB

in less than 10μs when loaded with 5kΩ in parallel with

200pF. The buffer amplifier is stable with any combination

of resistive loads greater than 5kΩ and capacitive loads

less than 200pF.

Program the input register bits to power-down the device.

The DAC registers are preserved during power-down

and upon wake-up, the DAC output is restored to its pre-

power-down voltage.

Power-On Reset

The MAX5712 has a POR circuit to set the DACs output to

zero when VDD is first applied. This ensures that unwanted

DAC output voltages will not occur immediately following a

system start-up, such as after a loss of power. Upon initial

power-up, an internal power-on-reset circuit ensures that

all DAC registers are cleared, the DAC is powered-down,

and its output is terminated to GND by a 100kΩ resistor.

An 8μs recovery time after issuing a wake-up command is

needed before writing to the DAC registers.

Digital Section

3-Wire Serial Interface

The MAX5712 digital interface is a standard 3-wire

connection compatible with SPI/QSPI/MICROWIRE/DSP

interfaces. The chip-select input (CS) frames the serial

data loading at DIN. Immediately following CS high-to-low

transition, the data is shifted synchronously and latched

into the input register on the falling edge of the serial clock

input (SCLK). After 16 bits have been loaded into the seri-

al input register, it transfers its contents to the DAC latch.

CS may then either be held low or brought high. CS must

be brought high for a minimum of 80ns before the next

write sequence, since a write sequence is initiated on a

falling edge of CS. Not keeping CS low during the first 15

SCLK cycles discards input data. The serial clock (SCLK)

can idle either high or low between transitions. Figure 1

shows the complete 3-wire serial interface transmission.

Table 1 lists serial-interface mapping.

SCLK

CS

DIN

Figure 1. Timing Diagram

tCH

tCL

tCSW

tCSS

tDH

tDS

C3

tCSH

SO

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