MC100LVE111(2002) データシートの表示（PDF） - ON Semiconductor
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MC100LVE111 Datasheet PDF : 8 Pages
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MC100LVE111
900
9
800
8
700
7
600
6
500
5
400
4
300
1200ÉÉ000 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ(JITTÉÉER)ÉÉÉÉÉÉÉÉÉÉÉÉ
23ÉÉÉÉ
1
0
300 600 900 1200 1500 1800 2100 2400
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
Q
Driver
Device
Q
50 W
D
Receiver
Device
D
50 W
V TT
VTT = VCC – 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1503
AN1504
AN1560
AN1568
AN1596
AN1650
AN1672
AND8001
AND8002
AND8020
– ECLinPS Circuit Performance at Non–Standard VIH Levels
– ECL Clock Distribution Techniques
– Designing with PECL (ECL at +5.0 V)
– ECLinPS I/O SPICE Modeling Kit
– Metastability and the ECLinPS Family
– Low Voltage ECLinPS SPICE Modeling Kit
– Interfacing Between LVDS and ECL
– ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
– Using Wire–OR Ties in ECLinPS Designs
– The ECL Translator Guide
– Odd Number Counters Design
– Marking and Date Codes
– Termination of ECL Logic Devices
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