MC12210D データシートの表示（PDF） - LANSDALE Semiconductor Inc.
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MC12210D Datasheet PDF : 11 Pages
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ML12210
LANSDALE Semiconductor, Inc.
DATA ENTRY FORMAT
The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit programma-
ble reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock shifts one bit of serial
data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into the latch when load enable
pin is HIGH or OPEN.
Control bit: “H” = data is transferred into 15–bit latch of programmable reference divider
“L” = data is transferred into 18–bit latch of programmable divider
WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will affect
the VCO.
PROGRAMMABLE REFERENCE DIVIDER
16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If the con-
trol bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8 to16383) and
the prescaler divide ratio (SW=0 for ÷64/65, SW=1 for ÷32/33). An R divide ratio less than 8 is prohibited.
For Control bit (C) = HIGH:
SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT)
MSB
CONTROL BIT (LAST BIT)
LSB
SRRRRRRRRRRRRRRC
W 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE
REFERENCE COUNTER (R–COUNTER)
DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER
Divide
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Ratio R
14
13
12
11
10
9
8
7
6
5
4
3
2
1
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
0
0
0
0
0
0
0
0
1
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PRESCALER SELECT BIT
Prescaler Divide Ratio P
SW
64/65
0
32/33
1
Page 4 of 11
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