MC56F8323PB データシートの表示（PDF） - Motorola => Freescale

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MC56F8323PB

16-bit Hybrid Controller

Motorola => Freescale 

• FlexCAN (CAN Version 2.0 B-compliant) Module with 2-pin port for transmit and receive

• Up to two Serial Communication Interfaces (SCIs)

• Up to two Serial Peripheral Interfaces (SPIs)

• Computer-Operating Properly (COP)/Watchdog timer

• One dedicated external interrupt pin

• 27 General Purpose I/O (GPIO) pins

• Integrated Power-On Reset and Low-Voltage Interrupt Module

• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent,

real-time debugging

• Software-programmable, Phase Lock Loop (PLL)

• On-chip relaxation oscillator

1.1.4 Energy Information

• Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs

• On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

• Wait and Stop modes available

• ADC smart power management

• Each peripheral can be individually disabled to save power

1.2 56F8323 Description

The 56F8323 is a member of the 56800E core-based family of hybrid controllers. It combines, on a single

chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller

with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the 56F8323 is well-suited for many applications.

The 56F8323 includes many peripherals that are especially useful for applications such as automotive

control; industrial control and networking; motion control; home appliances; general purpose inverters;

smart sensors; fire and security systems; power management; and medical monitoring.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The

instruction set is also highly efficient for C Compilers to enable rapid development of optimized control

applications.

The 56F8323 supports program execution from internal memories. Two data operands can be accessed from

the on-chip data RAM per instruction cycle. The 56F8323 also provides one external dedicated interrupt

line and up to 27 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8323 controller includes 32KB of Program Flash and 8KB of Data Flash (each programmable

through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM. A total of 8KB words of Boot

Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used

to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can

be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash

page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased.

4

56F8323 Technical Data

MOTOROLA

Preliminary

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