MGP3006 データシートの表示（PDF） - Siemens AG

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MGP3006

GHz PLL with I2C Bus and Four Chip Addresses

Siemens AG 

MGP 3006X

Circuit Description (cont’d)

Bit Allocation

Address byte

MSB

A = Acknowledge

1

1

0

0

0 MA1 MA0 0

A

Prog. divider Byte 1

0 n14 n13 n12 n11 n10 n9 n8 A

Prog. divider Byte 2 n7 n6 n5 n4 n3 n2 n1 n0 A

Control info. Byte 1

1

5I T1 T0 1

1

1 OS A

Control info. Byte 2

P7 X X X X P2 P1 X A

Divider Ratio

N = 16384 × n14 + 8192 × n13 + 4096 × n12 + 2048 × n11 + 1024 × n10 + 512 × n9 +

256 × n8 + 128 × n7 + 64 × n6 + 32 × n5 + 16 × n4 + 8 × n3 + 4 × n2 + 2 × n1 + n0

Band Selection

P1, P2, P7 = 1

Open-collector output is active.

Pump Current Programming

5I = 1

High current

UD Disable

OS = 1

UD is disabled.

Test Mode

T1, T0 = 0, 0

T1 = 1

T0 = 1

Normal operation

P7 = carry Cy of programmable divider

Tristate: charge pump output PD is in high-impedance state.

Semiconductor Group

4

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