MH8S72BAFD-7 データシートの表示（PDF） - MITSUBISHI ELECTRIC
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MH8S72BAFD-7 Datasheet PDF : 56 Pages
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MH8S72BAFD -7, -8 MITSUBISHI LSIs
P rSepl iemci.n a r y 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
73-90
91-92
93-94
95-98
99-125
126
127
Precharge to Active Minimum
Row Active to Row Active Min.
RAS to CAS Delay Min
Active to Precharge Min
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
Checksum for bytes 0-62
Manufactures Jedec ID code per JEP-108E
Manufacturing location
Manufactures Part Number
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification detail for 100MHz support
20ns
20ns
20ns
50ns
64MByte
2ns
1ns
2ns
1ns
option
rev 1.2A
Check sum for -7
Check sum for -8
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
14
14
14
32
10
20
10
20
10
00
12
32
72
1CFFFFFFFFFFFFFF
01
02
03
04
MH8S72BAFD-7
4D4838533634424146442D37202020202020
MH8S72BAFD-8
PCB revision
4D4838533634424146442D38202020202020
rrrr
year/week code
yyww
serial number
ssssssss
option
00
-8
100MHz
64
-7
CK0,1,2,3,CL=2/3,AP
FF
-8
CK0,1,2,3,CL=3,AP
FD
128+
Unused storage locations
open
00
MIT-DS-0273-0.2
MITSUBISHI
ELECTRIC
1/ Dec./1998 5
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