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MPC185TS データシートの表示(PDF) - Motorola => Freescale

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MPC185TS
Motorola
Motorola => Freescale Motorola
MPC185TS Datasheet PDF : 12 Pages
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Freescale Semiconductor, Inc.
7.7 Random Number Generator (RNG)
The RNG is a digital integrated circuit capable of generating 32-bit random numbers. It is designed to
comply with FIPS 140-1 standards for randomness and non-determinism.
Because many cryptographic algorithms use random numbers as a source for generating a secret value (a
nonce), it is desirable to have a private RNG for use by the MPC185. The anonymity of each random number
must be maintained, as well as the unpredictability of the next random number. The FIPS-140 ‘common
criteria’ compliant private RNG allows the system to develop random challenges or random secret keys. The
secret key can thus remain hidden from even the high-level application code, providing an added measure
of physical security.
7.8 32KB General Purpose RAM (gpRAM)
The MPC185 contains 32KB of internal general purpose RAM that can be used to store keys, IVs and data.
The internal scratchpad allows the user to store frequently used context on chip which increases system
performance by minimizing setup time. This feature is especially important when dealing with small
packets and in systems where bus bandwidth is limited.
8 Performance Estimates
Bulk encryption/authentication performance estimates shown in Table 8-1 include data/key/context reads
(from memory to MPC185), security processing (internal to MPC185), and writes of completed
data/context to memory by MPC185, using typical 60x system overhead.
Table 8-1. Estimated Bulk Data Encryption Performance (Mbps)
DES
CBC
64 byte
128 byte
256 byte
512 byte
1024 byte
1536 byte
204
355
562
815
1051
1164
3DES
CBC
AES 128 AES 256
ARC4
168
180
260
281
358
391
449
489
513
557
538
585
153
102
239
176
332
279
415
404
473
521
497
595
MD5
177
311
472
636
770
828
SHA-1
3DES/
Kasumi HMAC-
SHA-1(Rx)
162
93
138
279
104
237
411
230
350
540
316
459
639
391
544
681
426
579
The MPC185 supports single pass processing of encryption/message authentication. All performance
measurements assume standard memory latency, and unconstrained use of an 83Mhz, 64-bit bus utilizing
the 60x bus protocol.
9 Revision History
Table 9-1 summarizes the revision history of this document.
10
MPC185 Security Processor Technical Summary
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com

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