MPC185TS データシートの表示（PDF） - Motorola => Freescale

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MPC185TS

Security Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

PowerPC-architectured processor and memory controller. The ability of the MPC185 to be a master on the

60x bus allows the co-processor to offload the data movement bottleneck normally associated with slave

devices.

The host processor accesses the MPC185 through its device drivers using system memory for data storage.

The MPC185 resides in the memory map of the processor, therefore when an application requires

cryptographic functions, it simply creates descriptors for the MPC185 which define the cryptographic

function to be performed and the location of the data. The MPC185’s 60x-mastering capability permits the

host processor to set up a crypto-channel with a few short register writes, leaving the MPC185 to perform

reads and writes on system memory to complete the required task.

EEPROM

MPC185

60x Bus

MPC82xx

PCI or Local Bus

Main

Memory

I/O or Network

Interface

Figure 4-1. MPC185 Connected to PowerQuicc II 60xBus

Figure 4-2 shows a configuration with the MPC185 communicating with the host processor via a PCI

bridge, such as the MPC107.

MPC7xx, MPC74xx

60x Bus

MPC185

MPC107

PCI Bridge

PCI Local Bus

Main

Memory

Network

Interface Card

PCI

Application

Network

Interface Card

Figure 4-2. MPC185 Connected to host CPU via a Bridge

MOTOROLA

MPC185 Security Processor Technical Summary

3

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